SLUUCC4A October 2020 – September 2021 TPS92520-Q1
The SPI command box allows register read and write actions and it also records the SPI status sequentially.
Figure 6-12 SPI Command WindowTo ensure a connection from the board to the TPS92520-Q1 exists, perform the following steps as shown in Figure 6-12.
The default value of 0x07 for the register 11 will be shown in the SPI Status window, see Figure 6-13.
Figure 6-13 SPI Read Example. To write data to associated register address:
Figure 6-14 SPI Write Example.