SLUUD92 June   2025 UCC218200-Q1

 

  1.   1
  2.   Abstract
  3. 1General TI High Voltage Evaluation User Safety Guidelines
  4. 2Module and Gate Driver Compatibility
    1. 2.1 Supported Wolfspeed Modules and Evaluation Platforms
    2. 2.2 Supported Gate Drivers
  5. 3System Overview and Functions
    1. 3.1 Features
    2. 3.2 Specifications
    3. 3.3 PCB Pinout
    4. 3.4 EVM Information
      1. 3.4.1 Primary-Side Power
      2. 3.4.2 Primary-Side I/O and Diagnostics
      3. 3.4.3 Secondary-Side Bias Supply
      4. 3.4.4 Output Stage Gate Loop
      5. 3.4.5 Current Booster
      6. 3.4.6 Short-Circuit Detection System
        1. 3.4.6.1 Short-Circuit Detection - DESAT
        2. 3.4.6.2 Short-Circuit Detection - OC
  6. 4Using the EVM
    1. 4.1 Equipment List and Board Setup
    2. 4.2 Test Setups and Procedures
      1. 4.2.1 Power-On and Bias Supply Check
      2. 4.2.2 Output Switching
  7. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  8. 6Additional Information
    1. 6.1 Trademarks
  9. 7Revision History

3.4.6.2 Short-Circuit Detection - OC

This EVM implemented to configure for OC detection as well for the future variants which can support OC short circuit detection approach instead of DESAT. The Vds voltage detection threshold can be calculated with the equation below mentioned

Equation 2. VDET⁡= VOCTH×R2+R3R3-VZ-n× VF

With the 0.7-V internal OC detection threshold, the two STTH122A diode with forward voltage of 0.6 V each, R2 = 1K Ω, R2=5K Ω, and R3 = 590 Ω, the Vds DESAT detection threshold is calculated to be 5.43 V. This detection threshold is valid for VDD = 15 V. If another Vds voltage detection threshold is desired, the R1, R2, R3, Cblk and the diodes values can be adjusted to update voltage detection threshold.

With a 100-pF blanking capacitor, the blanking time is calculated to be 40 ns. This blanking time is valid for VDD = 15 V.

UCC218002QEVM-111 OC CircuitFigure 3-7 OC Circuit