SLVSHD9A March   2025  – December 2025 DRV8001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RHA package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Sense Output (IPROPI)
      6. 7.4.6 Protection Circuits
        1. 7.4.6.1 Fault Reset (CLR_FLT)
        2. 7.4.6.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.6.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.6.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.6.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.6.6 Thermal Clusters
        7. 7.4.6.7 Watchdog Timer
        8. 7.4.6.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8001-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

7.4.4.1 Half-bridge Control

The half-bridge drivers can be controlled in two modes to support control schemes with either PWM input pins or SPI register control. The half-bridge drivers also have configuration registers (HB_OUT_CNFG1 and HB_OUT_CNFG2) to enable half-bridge control and to set up control mode (PWM or SPI).

The half-bridges can be configured for control by input signal from either PWM1 or PWM2 pins. The signal to PWM1 pin can be multiplexed internally to half-bridges, high-side drivers, and heater driver. PWM2 control from PWM2 pin is only available for half-bridges. Each half-bridge driver's slew rate can be configured in the HB_SR_CNFG.

The configuration table is shown below. Note that OUT5 and OUT6 are configured in HB_OUT_CNFG1 and OUT1 through OUT4 are configured in HB_OUT_CNFG2:

Table 7-22 OUTX_CNFG Half-bridge Configuration
OUTX_CNFG[2] OUTX_CNFG[1] OUTX_CNFG[0] OUTx HS ON LS ON
0 0 0 OFF OFF OFF
0 0 1 SPI Register Control OUTX_CTRL OUTX_CTRL
0 1 0 PWM 1 Complementary Control ~PWM1 PWM1
0 1 1 PWM 1 LS Control OFF PWM1
1 0 0 PWM 1 HS Control PWM1 OFF
1 0 1 PWM 2 Complementary Control ~PWM2 PWM2
1 1 0 PWM 2 LS Control OFF PWM2
1 1 1 PWM 2 HS Control PWM2 OFF

When the half-bridges are configured for SPI register control (OUTx_CNFG = 01b), the half-bridges high- and low-side MOSFETs can be individually controlled in register HB_CTRL with bits OUTx_CTRL. The control truth table for the half-bridge outputs is shown below:

Table 7-23 Half-bridge Driver Controls
OUTx_CTRL (OUT1-6) bits Configuration Description
00 OFF Half-bridge control OFF
01 HS ON High-side MOSFET ON
10 LS ON Low-side MOSFET ON
11 RSVD Reserved.

The half-bridge control mode can be changed anytime SPI communication is available by writing to the bits. This change is immediately reflected.

When the half-bridges are configured for PWM operation (OUTx_CNFG = 01xb, 10xb or 11xb), the inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive modes.

The device automatically generates the dead-time needed during transitioning between the high-side and low-side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage. No external timing is required. This scheme provides minimum dead time while preventing shoot-through current.