SLVSHM2A March   2025  – August 2025 TPS2HC120-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Current and Voltage Conventions
      2. 7.3.2 Low Power Mode
      3. 7.3.3 Accurate Current Sense
      4. 7.3.4 Adjustable Current Limit
      5. 7.3.5 Inductive-Load Switching-Off Clamp
      6. 7.3.6 Fault Detection and Reporting
        1. 7.3.6.1 Diagnostic Enable Function
        2. 7.3.6.2 Multiplexing of Current Sense
        3. 7.3.6.3 FAULT Reporting
        4. 7.3.6.4 Fault Table
      7. 7.3.7 Full Diagnostics
        1. 7.3.7.1 Short-to-GND and Overload Detection
        2. 7.3.7.2 Open-Load Detection
          1. 7.3.7.2.1 Channel On
          2. 7.3.7.2.2 Channel Off
        3. 7.3.7.3 Short-to-Battery Detection
        4. 7.3.7.4 Reverse-Polarity and Battery Protection
        5. 7.3.7.5 Thermal Fault Detection
          1. 7.3.7.5.1 Thermal Protection Behavior
      8. 7.3.8 Full Protections
        1. 7.3.8.1 UVLO Protection
        2. 7.3.8.2 Loss of GND Protection
        3. 7.3.8.3 Loss of Power Supply Protection
        4. 7.3.8.4 Reverse Battery Protection
        5. 7.3.8.5 Protection for MCU I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 EMC Transient Disturbances Test
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
        1. 8.5.2.1 Without a GND Network
        2. 8.5.2.2 With a GND Network
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.7 Switching Characteristics

VBB = 13.5 V, TJ = –40°C to +150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDR Channel Turn-on delay time (from Active) VBB = 13.5V, RL = 1kΩ 50% of EN to 10% of VOUT 30 55 µs
Channel Turn-on delay time (from Sleep or LPM) 40 60 µs
tDF Channel Turn-off delay time (from Active) VBB = 13.5V, RL = 100Ω 50% of EN to 90% of VOUT 30 55 µs
Channel Turn-off delay time (from LPM) VBB = 13.5V, RL = 1kΩ 50% of EN to 90% of VOUT 55 85 µs
SRR VOUT rising slew rate VBB = 13.5V, 20% to 80% of VOUT,
RL = 100Ω		 0.1 0.3 0.5 V/µs
SRF VOUT falling slew rate VBB = 13.5V, 80% to 20% of VOUT,
RL = 100Ω		 0.1 0.3 0.5 V/µs
fmax Maximum PWM frequency 2 kHz
tON Channel Turn-on time (STANDBY DELAY to ACTIVE) VBB = 13.5 V, RL = 100Ω  50% of EN to 80% of VOUT 30 50 145 µs
tOFF Channel Turn-off time (ACTIVE to STANDBY DELAY) VBB = 13.5V, RL = 100Ω  50% of EN to 20% of VOUT 30 70 145 µs
tON - tOFF  Turn-on and off matching 1ms enable pulse VBB = 13.5V, RL = 100Ω –40 40 µs
200-µs enable pulse, VBB = 13.5V, RL = 100Ω,
 		 –40 40 µs
ΔPWM  PWM accuracy - average load current 200-µs enable pulse (1ms period), VBB = 13.5V, RL = 100Ω 
 		 –25 25 %
≤500Hz, 50% Duty cycle VBB = 13.5V, RL = 100Ω 
 		 –12 12 %
EON Switching energy losses during turn-on VBB = 13.5V, RL = 100Ω 0.5 mJ
EOFF Switching energy losses during turn-off VBB = 13.5V, RL = 100Ω 0.5 mJ