SLVSI46 July   2025 DRV8818A

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7.     13
    8. 5.7 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PWM H-Bridge Drivers
      2. 6.3.2 Current Regulation
      3. 6.3.3 Decay Mode
      4. 6.3.4 Microstepping Indexer
      5. 6.3.5 Protection Circuits
        1. 6.3.5.1 Overcurrent Protection (OCP)
        2. 6.3.5.2 Thermal Shutdown (TSD)
        3. 6.3.5.3 Undervoltage Lockout (UVLO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Disable Mode
      3. 6.4.3 Active Mode
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Stepper Motor Speed
        2. 7.2.2.2 Current Regulation VREF and RSENSE
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Heat Sinking
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
        1. 7.4.3.1 Power Dissipation
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Documentation Support
      1. 8.6.1 Related Documentation
  10.   Mechanical, Packaging, and Orderable Information

6.4.3 Active Mode

After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the SLEEPn pin is logic high, and tWAKE has elapsed, the device enters active operating mode. In this mode, the H-Bridge, charge pump, and internal logic are active and the device is ready to receive inputs.

This mode is enabled when -

  • SLEEPn pin is logic high

  • ENABLEn pin is logic low

  • RESETn pin is logic high

  • VM > VUVLO for VM

  • VCC > VUVLO for VCC
The tWAKE time must elapse before the device is ready for inputs.