SLVSI75 May   2026 DRV8218

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Transient Current Capability
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Control Modes
        1. 7.4.1.1 PWM Control Mode (MODE = 0)
        2. 7.4.1.2 PH/EN Control Mode (MODE = 1)
        3. 7.4.1.3 Independent Half-Bridge Control Mode (MODE = Hi-Z)
      2. 7.4.2 Pin Diagrams
        1. 7.4.2.1 Logic-Level Inputs
        2. 7.4.2.2 Tri-Level Input
      3. 7.4.3 Protection Circuits
        1. 7.4.3.1 Supply Undervoltage Lockout (UVLO)
        2. 7.4.3.2 OUTx Overcurrent Protection (OCP)
        3. 7.4.3.3 Thermal Shutdown (TSD)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Active Mode
      2. 7.5.2 Low-Power Sleep Mode
      3. 7.5.3 Fault Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Full-Bridge Driving
        1. 8.2.1.1 Supply Voltage
        2. 8.2.1.2 Control Interface - Full Bridge
        3. 8.2.1.3 Low-Power Operation
        4. 8.2.1.4 Application Curves
      2. 8.2.2 Half-Bridge Driving
        1. 8.2.2.1 Control Interface
        2. 8.2.2.2 Low-Power Operation
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Parallel Multiple Drivers
      4. 8.2.4 Dual-Coil Relay Driving
        1. 8.2.4.1 Control Interface
        2. 8.2.4.2 Low-Power Operation
        3. 8.2.4.3 Application Curves
      5. 8.2.5 Current Sense
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
          1. 8.2.5.2.1 Shunt Resistor Sizing
          2. 8.2.5.2.2 RC Filter
    3. 8.3 Current Capability and Thermal Performance
      1. 8.3.1 Power Dissipation and Output Current Capability
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Bulk Capacitance
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

7.5.2 Low-Power Sleep Mode

The DRV8218 supports a low-power sleep mode to reduce current consumption from VM and VCC when the driver is not active. There are two ways to enter low-power sleep mode: autosleep and using the VCC pin. In autosleep mode, the device draws minimal current denoted by IVCCQ and IVMQ. In VCC sleep mode, the device draws minimal current denoted by IVMQ_UV and IVCCQ_UV since the device is in undervoltage lockout (UVLO) with VCC below the UVLO threshold.

DRV8218 Sleep Mode Entry and Wakeup Timing Diagram Figure 7-6 Sleep Mode Entry and Wakeup Timing Diagram

Autosleep

Table 7-7 describes how to enter low-power sleep mode for PWM control mode and PH/EN control mode.

Table 7-7 Autosleep mode summary
Input pin state OUT1 OUT2 Description Exit/Wake
MODE = 0, IN1 = IN2 = 0 Hi-Z Hi-Z Autosleep for PWM or half-bridge interface: Upon entering this state, the outputs are disabled. The device remains in Active Mode for tAUTOSLEEP, then goes into low-power mode. IN1 = 1 or IN2 = 1
MODE = 1, EN = 0 L → Hi-Z L → Hi-Z Autosleep for PH/EN interface: Upon entering this state, both outputs go into brake mode by turning the low-side FETs on. The device remains in this state for tAUTOSLEEP, then goes into low-power mode. Once in low-power mode, the outputs are disabled. EN = 1

The device returns to active mode when the input pins move to a state other than the ones in Table 7-7. To wake up the device from autosleep mode, the INx pins or EN pin (depending on MODE state) must be asserted high for longer than tWAKE before receiving PWM input signals.

VCC = 0V UVLO Sleep Mode

Table 7-8 VCC supply as sleep pin summary
Input pin state OUT1 OUT2 Description Exit/Wake
VCC = 0V, MODE = 0 (PWM) UVLO (Hi-Z) UVLO (Hi-Z) The VCC pin can be powered from a GPIO pin to control device sleep. Driving the GPIO low pulls VCC below the UVLO threshold, placing the device into low-power mode and setting all outputs to Hi-Z. See Section 8.2.2.2 for details. VCC > VUVLO, then IN1 or IN2 = 1 for tWAKE
VCC = 0V, MODE = 1 (PH/EN) UVLO (Hi-Z) UVLO (Hi-Z) VCC > VUVLO, then EN = 1 for tWAKE
VCC = 0V, MODE = Hi-Z (Half-Bridge) UVLO (Hi-Z) UVLO (Hi-Z) VCC > VUVLO, then IN1 or IN2 = 1 for tWAKE.

To wake up the device from VCC sleep mode, the VCC pin voltage must be greater than VUVLO,VCC. Once the VCC pin has a valid voltage, either or both INx pins must be asserted high for longer than tWAKE to fully wake up the device. To protect the microcontroller GPIO pin from excess current due to the decoupling capacitor charging current, a resistor can be added between the GPIO and the decoupling capacitor on the VCC pin. See Section 8.2.2.2 for more information on designing this limiting resistor.

For the lowest supply current draw, set all input pins to logic low to eliminate current draw through the pulldown resistors in sleep mode. If the MODE pin is set to Hi-Z or logic low, the pin does not draw current in sleep mode. However, the MODE pin draws some current in sleep mode when set to logic high.