SLVSI75 May   2026 DRV8218

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Transient Current Capability
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Control Modes
        1. 7.4.1.1 PWM Control Mode (MODE = 0)
        2. 7.4.1.2 PH/EN Control Mode (MODE = 1)
        3. 7.4.1.3 Independent Half-Bridge Control Mode (MODE = Hi-Z)
      2. 7.4.2 Pin Diagrams
        1. 7.4.2.1 Logic-Level Inputs
        2. 7.4.2.2 Tri-Level Input
      3. 7.4.3 Protection Circuits
        1. 7.4.3.1 Supply Undervoltage Lockout (UVLO)
        2. 7.4.3.2 OUTx Overcurrent Protection (OCP)
        3. 7.4.3.3 Thermal Shutdown (TSD)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Active Mode
      2. 7.5.2 Low-Power Sleep Mode
      3. 7.5.3 Fault Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Full-Bridge Driving
        1. 8.2.1.1 Supply Voltage
        2. 8.2.1.2 Control Interface - Full Bridge
        3. 8.2.1.3 Low-Power Operation
        4. 8.2.1.4 Application Curves
      2. 8.2.2 Half-Bridge Driving
        1. 8.2.2.1 Control Interface
        2. 8.2.2.2 Low-Power Operation
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Parallel Multiple Drivers
      4. 8.2.4 Dual-Coil Relay Driving
        1. 8.2.4.1 Control Interface
        2. 8.2.4.2 Low-Power Operation
        3. 8.2.4.3 Application Curves
      5. 8.2.5 Current Sense
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
          1. 8.2.5.2.1 Shunt Resistor Sizing
          2. 8.2.5.2.2 RC Filter
    3. 8.3 Current Capability and Thermal Performance
      1. 8.3.1 Power Dissipation and Output Current Capability
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Bulk Capacitance
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

7.4.3.2 OUTx Overcurrent Protection (OCP)

An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short circuit events. If the output current exceeds the overcurrent threshold, IOCP, for longer than the overcurrent deglitch time, tOCP, all MOSFETs in the H-bridge are disabled. After tRETRY, the MOSFETs are re-enabled according to the state of the PH/IN1 and EN/IN2 pins. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes.

In half-bridge control mode, the OCP behavior is slightly modified. If an overcurrent event is detected, only the corresponding half-bridge is disabled. The other half-bridge continues normal operation. This allows for the device to manage independent fault events when driving independent loads. If an overcurrent event is detected in both half-bridges, both half-bridges are disabled. Both half-bridges share the same overcurrent retry timer. If an overcurrent event occurs first in OUT1, that output is disabled for the duration of tRETRY. If OUT2 experiences an overcurrent event after OUT1, but before tRETRY has expired, then both OUTx pins remain disabled for a full duration of tRETRY.

DRV8218 OCP Operation Figure 7-5 OCP Operation