SLVSIB0 December   2025 UCD91320

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Linearity Parameters
    7. 5.7 POR and BOR
    8. 5.8 Low Frequency Crystal/Clock
    9. 5.9 Flash Memory Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Feature Description
      1. 6.2.1 TI Sequencer Studio Software
      2. 6.2.2 PMBUS Interface
      3. 6.2.3 PMBUS Security
    3. 6.3 Device Functional Modes
      1. 6.3.1 Black Box Fault Logging
      2. 6.3.2 PMBus Address Selection
      3. 6.3.3 Brownout
    4.     Failure Analysis and Returns
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
  9. Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Pin Configuration and Functions

UCD91320 PZ Package 100-Pin LQFP Top ViewFigure 4-1 PZ Package 100-Pin LQFP Top View
UCD91320 ZAW Package 100-Pin nFBGA Top ViewFigure 4-2 ZAW Package 100-Pin nFBGA Top View
Table 4-1 Pin Functions

PIN

TYPE

DESCRIPTION

NAME

100-QFP

100-nFBGAPin ID

MONITORING INPUTS (MONx)

MON1

99

B2

I/O

1

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON2

98

C2

I/O

2

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON3

94

D1

I/O

3

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON4

93

E2

I/O

4

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON5

95

C1

I/O

5

Analog or Digital Monitor (0V – 3.3V)

MON6

86

F2

I/O

6

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON7

82

F3

I/O

7

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON8

53

K8

I/O

8

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON9

54

K7

I/O

9

Analog Monitor (0V – 3.3V)(1)

MON10

55

H7

I/O

10

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON11

69

K4

I/O

11

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON12

70

K3

I/O

12

Analog Monitor (0V – 3.3V)(1)

MON13

73

K2

I/O

13

Analog or Digital Monitor (0V – 3.3V), or GPIO

MON14

74

K1

I/O

14

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON1575J1

I/O

15

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON1677H2

I/O

16

Analog Monitor (0V – 3.3V)(1)
MON1751J10

I/O

17

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON1852K10

I/O

18

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON1971J4

I/O

19

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON2072J3

I/O

20

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON2184H1

I/O

21

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON2285G1

I/O

22

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON2396B1

I/O

23

Analog or Digital Monitor (0V – 3.3V), or GPIO
MON2497D2I/O

24

Analog or Digital Monitor (0V – 3.3V), or GPIO
Digital Monitoring (DMONx)
DMON189E4I/O

25

Digital Monitor (0V – 3.3V), or GPIO
DMON290F1I/O

26

Digital Monitor (0V – 3.3V), or GPIO
DMON391E3I/O

27

Digital Monitor (0V – 3.3V), or GPIO
DMON480G4I/O

28

Digital Monitor (0V – 3.3V), or GPIO
DMON581F4I/O

29

Digital Monitor (0V – 3.3V), or GPIO
DMON666H4I/O

30

Digital Monitor (0V – 3.3V), or GPIO
DMON714D6I/O

31

Digital Monitor (0V – 3.3V), or GPIO
DMON878H3I/O

32

Digital Monitor (0V – 3.3V), or GPIO

Rail Enables (ENx)

EN1(GPIO)

22

B7

I/O

33

Rail enable signal, digital output, or GPIO

EN2(GPIO)

21

C7

I/O

34

Rail enable signal, digital output, or GPIO

EN3(GPIO)

24

D8

I/O

35

Rail enable signal, digital output, or GPIO

EN4(GPIO)

26

B8

I/O

36

Rail enable signal, digital output, or GPIO

EN5(GPIO)

20

C6

I/O

37

Rail enable signal, digital output, or GPIO

EN6(GPIO)

19

A9

I/O

38

Rail enable signal, digital output, or GPIO

EN7(GPIO)

18

A8

I/O

39

Rail enable signal, digital output, or GPIO

EN8(GPIO)

42

F9

I/O

40

Rail enable signal, digital output, or GPIO

EN9(GPIO)

47

H10

I/O

41

Rail enable signal, digital output, or GPIO

EN10(GPIO)

48

J9

I/O

42

Rail enable signal, digital output, or GPIO

EN11(GPIO)

37

F6

I/O

43

Rail enable signal, digital output, or GPIO

EN12(GPIO)

39

F7

I/O

44

Rail enable signal, digital output, or GPIO

EN13(GPIO)

5

D4

I/O

45

Rail enable signal, digital output, or GPIO

EN14(GPIO)

15

A5

I/O

46

Rail enable signal, digital output, or GPIO

EN15(GPIO)

43

G7

I/O

47

Rail enable signal, digital output, or GPIO

EN16(GPIO)

46

G10

I/O

48

Rail enable signal, digital output, or GPIO

EN17(GPIO)10C5

I/O

49

Rail enable signal, digital output, or GPIO

EN18(GPIO)11B5

I/O

50

Rail enable signal, digital output, or GPIO

EN19(GPIO)12D5

I/O

51

Rail enable signal, digital output, or GPIO

EN20(GPIO)35E6

I/O

52

Rail enable signal, digital output, or GPIO

EN21(GPIO)38C10

I/O

53

Rail enable signal, digital output, or GPIO

EN22(GPIO)58H9

I/O

54

Rail enable signal, digital output, or GPIO

EN23(GPIO)61J6

I/O

55

Rail enable signal, digital output, or GPIO

EN24(GPIO)62J5

I/O

56

Rail enable signal, digital output, or GPIO

EN25(GPIO)65H5

I/O

57

Rail enable signal, digital output, or GPIO

EN26(GPIO)67G6

I/O

58

Rail enable signal, digital output, or GPIO

EN27(GPIO)36B10

I/O

59

Rail enable signal, digital output, or GPIO

EN28(GPIO)60K5

I/O

60

Rail enable signal, digital output, or GPIO

EN29(GPIO)45G9

I/O

61

Rail enable signal, digital output, or GPIO

EN30(GPIO)44F10

I/O

62

Rail enable signal, digital output, or GPIO

EN31(GPIO)79G3

I/O

63

Rail enable signal, digital output, or GPIO

EN32(GPIO)68G5

I/O

64

Rail enable signal, digital output, or GPIO

Closed-Loop Margin Pins (MARx)

MAR1(GPIO)

23

C8

I/O

65

Closed-loop margin PWM output, or GPIO

MAR2(GPIO)

28

C9

I/O

66

Closed-loop margin PWM output, or GPIO

MAR3(GPIO)

25

D9

I/O

67

Closed-loop margin PWM output, or GPIO

MAR4(GPIO)

27

D10

I/O

68

Closed-loop margin PWM output, or GPIO

MAR5(GPIO)

33

E7

I/O

69

Closed-loop margin PWM output, or GPIO

MAR6(GPIO)

34

E9

I/O

70

Closed-loop margin PWM output, or GPIO

MAR7(GPIO)

40

E10

I/O

71

Closed-loop margin PWM output, or GPIO

MAR8(GPIO)

41

F8

I/O

72

Closed-loop margin PWM output, or GPIO

MAR9(GPIO)56J7

I/O

73

Closed-loop margin PWM output, or GPIO

MAR10(GPIO)57H8

I/O

74

Closed-loop margin PWM output, or GPIO

MAR11(GPIO)87F5

I/O

75

Closed-loop margin PWM output, or GPIO

MAR12(GPIO)88E5

I/O

76

Closed-loop margin PWM output, or GPIO

MAR13(GPIO)29E8

I/O

77

Closed-loop margin PWM output, or GPIO

MAR14(GPIO)30B9

I/O

78

Closed-loop margin PWM output, or GPIO

MAR15(GPIO)31D7

I/O

79

Closed-loop margin PWM output, or GPIO

MAR16(GPIO)32A10

I/O

80

Closed-loop margin PWM output, or GPIO

General Purpose Inputs and Outputs (GPIOx)

GPIO149G8I/O

81

Boolean-Logical Output, or GPIO
GPIO250J8

I/O

82

Boolean-Logical Output, or GPIO

PMBus COMM INTERFACE

PMBUS_CLK

7

A3

I/O

N/A

PMBus clock (must have pullup to 3.3V)

PMBUS_DATA

3

C3

I/O

N/A

PMBus data (must have pullup to 3.3V)

PMBUS_nALERT

2

C4

O

N/A

PMBus alert, active-low, open-drain output (must have pullup to 3.3V)

PMBUS_CNTRL

1

D3

I

N/A

PMBus control (must have pullup to 3.3V)

PMBUS_ADDR083G2IN/APMBUS Address Select
PMBUS_ADDR113B6IN/APMBUS Address Select
PMBUS_ADDR259H6IN/APMBUS Address Select

INPUT POWER, GROUNDS, AND CLOCKING

LFXOUT

17

A7

CLK

N/A

Low-frequency crystal out

LFXIN

16

A6

CLK

N/A

Low-frequency crystal in

nRESET

6

B4

I

N/A

Active-low device reset input. Recommend pulling up to VDD if not required by application. Hold low for at least 1.5μs to perform a boot reset, or 1s for a power-on-reset (POR)

SYNC_OUT

4

B3

O

N/ASynchronization clock I/O (5kHz) for multiple chip cascading

VREF+

92

E1

I

N/A(Optional) positive node of external reference voltage

VREF-

76

J2

P

N/A(Optional) negative node of external reference voltage(1)

VDD

8,64

A4, K6

P

N/A

Input 3V to 3.6V supply. Refer to the Layout Guidelines section

VSS

9,63

A2, K9

P

N/A

Device ground

BPCAP

100

A1

P

N/A

0.47µF bypass capacitor. Refer to the Layout Guidelines section

Utilize MON9 only as an analog monitoring pin.

Utilize MON12 only as an analog monitoring pin.

Utilize MON16 only as an analog monitoring pin.

When the VREF- pin is not utilized, connect it to ground.