SLVSIM9 September   2025 LM5125A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Device and Phase Enable/Disable (UVLO/EN, EN2)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Determine the Total Phase Number
        2. 7.2.2.2  Determining the Duty Cycle
        3. 7.2.2.3  Timing Resistor RT
        4. 7.2.2.4  Inductor Selection Lm
        5. 7.2.2.5  Current Sense Resistor Rcs
        6. 7.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.2.7  Low-Side Power Switch QL
        8. 7.2.2.8  High-Side Power Switch QH
        9. 7.2.2.9  Snubber Components
        10. 7.2.2.10 Vout Programming
        11. 7.2.2.11 Input Current Limit (ILIM/IMON)
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 Soft Start
        14. 7.2.2.14 CFG Settings
        15. 7.2.2.15 Output Capacitor Cout
        16. 7.2.2.16 Input Capacitor Cin
        17. 7.2.2.17 Bootstrap Capacitor
        18. 7.2.2.18 VCC Capacitor CVCC
        19. 7.2.2.19 BIAS Capacitor
        20. 7.2.2.20 VOUT Capacitor
        21. 7.2.2.21 Loop Compensation
      3. 7.2.3 Application Curves
        1. 7.2.3.1 Efficiency
        2. 7.2.3.2 Steady State Waveforms
        3. 7.2.3.3 Step Load Response
        4. 7.2.3.4 Sync Operation
        5. 7.2.3.5 AC Loop Response Curve
        6. 7.2.3.6 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)

Monitor the average VI input current at the IMON-pin. The average sensed current of each active phase is summed up generating a source current at the IMON-pin, which is converted to a voltage by the resistor RIMON. The resulting voltage VIMON is calculated according to Equation 18, the required resistor RIMON according to Equation 17. VIMON regulates up to 3V and is self-protecting not reaching the absolute maximum value.

Equation 17. RIMON= VIMON(RCS1+RCS2) ×n×IIN×GIMON+n×IOFFSET
Equation 18. VIMON= ((RCS1+RCS2)×n×IIN×GIMON+n×IOFFSET)×RIMON

RCS1 and RCS2 are the respective phase sense resistors. For a disabled phase use 0Ω as sense resistor value, add additional sense resistor values for each active phase in dual device configuration. IIN is the input current, GIMON the transconductance gain, n the number of active phases and IOFFSET the offset current given in the electrical characteristics table.

Limit the average input current by choosing an appropriate resistor connected to the ILIM-pin. When the input current limit is active, VOUT is regulated down until the set average input current limit is reached. In case VOUT is regulated below the VI voltage the current is unlimited. The DLY-pin capacitor CDLY adds an additional delay time tDLY to activate and deactivate the average input current limit (see Figure 6-23). When the ILIM-pin voltage reaches the threshold VILIM (typical 1V) the source current IDLY is activated charging up the DLY-pin capacitor CDLY. The DLY-pin voltage VDLY rises until VDLY_peak_rise is reached, which activates the average input current limit. The ILIM-pin voltage is regulated to VILIM and the input current is regulated down to the average input current limit set by RILIM resulting in a VOUT drop. To exit the average current limit regulation the output load has to decrease, which causes VOUT to rise and VILIM to fall below VILIM_reset (typical 0.88V). VILIM_reset activates the sink current IDLY, which discharges the DLY-pin capacitor CDLY. When VDLY reaches VDLY_peak_fall the average input current limit is deactivated and the DLY-pin is discharged to VDLY_valley. The required resistor RILIM is calculated according to Equation 19.

Equation 19. RILIM= 1V(RCS1+RCS2)×n×IIN_LIM×GIMON+n×IOFFSET
Equation 20. tDLY= 2.6 ×CDLY5×10-6
Equation 21. CDLY=tDLY×5×10-62.6
LM5125A-Q1 Average Current Limit Figure 6-23 Average Current Limit