SLVSIM9 September   2025 LM5125A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Device and Phase Enable/Disable (UVLO/EN, EN2)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Determine the Total Phase Number
        2. 7.2.2.2  Determining the Duty Cycle
        3. 7.2.2.3  Timing Resistor RT
        4. 7.2.2.4  Inductor Selection Lm
        5. 7.2.2.5  Current Sense Resistor Rcs
        6. 7.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.2.7  Low-Side Power Switch QL
        8. 7.2.2.8  High-Side Power Switch QH
        9. 7.2.2.9  Snubber Components
        10. 7.2.2.10 Vout Programming
        11. 7.2.2.11 Input Current Limit (ILIM/IMON)
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 Soft Start
        14. 7.2.2.14 CFG Settings
        15. 7.2.2.15 Output Capacitor Cout
        16. 7.2.2.16 Input Capacitor Cin
        17. 7.2.2.17 Bootstrap Capacitor
        18. 7.2.2.18 VCC Capacitor CVCC
        19. 7.2.2.19 BIAS Capacitor
        20. 7.2.2.20 VOUT Capacitor
        21. 7.2.2.21 Loop Compensation
      3. 7.2.3 Application Curves
        1. 7.2.3.1 Efficiency
        2. 7.2.3.2 Steady State Waveforms
        3. 7.2.3.3 Step Load Response
        4. 7.2.3.4 Sync Operation
        5. 7.2.3.5 AC Loop Response Curve
        6. 7.2.3.6 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.1 Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)

The CFG0-pin defines the minimum dead time and the ATRK/DTRK-pin 20μA current. The levels shown in Table 6-1 are selected by the specified resistors in the Specifications section. When VOUT is programmed with a resistor turn the 20μA ATRK-pin current on, for voltage tracking turn the ATRK-pin current off.

Table 6-1 CFG0-pin Settings
Level Dead Time [ns] 20μA ATRK Current
1 14 on
2 30 on
3 50 on
4 75 on
5 100 on
6 125 on
7 150 on
8 200 on
9 14 off
10 30 off
11 50 off
12 75 off
13 100 off
14 125 off
15 150 off
16 200 off

The CFG1-pin setting defines the VOUT overvoltage protection level, Clock Dithering, the 120% input current limit protection (ICL_latch) operation, and the power-good pin behavior.

OVP bit 0: OVP bit 1 and 0 set the VOUT overvoltage protection level. [00] = 64V, [01] = 50V, [10]= 35V or [11] = 28.5V.
Clock Dithering: Enables dual random spread spectrum (DRSS) clock dithering or disables clock dithering.
ICL_latch: When ICL_latch is enabled and the peak current limit is exceeded by 20% the device goes to the Shutdown State (turns off and is latched). If ICL_latch is disabled the device stays active and tries to limit the inductor current at peak current limit.
PGOODOVP_enable: When PGOODOVP_enable is enabled the PGOOD-pin is pulled low for VOUT above OVP (Overvoltage Protection) or below the UV (Undervoltage) threshold. If PGOODOVP_enable is disabled the PGOOD-pin is only pulled low when VOUT is below UV (Undervoltage) threshold.
Table 6-2 Overvoltage Protection Level Selection
OVP Level OVP Bit 1 OVP Bit 0
64V 0 0
50V 0 1
35V 1 0
28.5V 1 1
Table 6-3 CFG1-pin Settings
Level OVP Bit 0 Clock Dithering Mode ICL_latch PGOODOVP_enable
1 0 enabled (DRSS) disabled disabled
2 1 enabled (DRSS) disabled disabled
3 0 enabled (DRSS) disabled enabled
4 1 enabled (DRSS) disabled enabled
5 0 enabled (DRSS) enabled disabled
6 1 enabled (DRSS) enabled disabled
7 0 enabled (DRSS) enabled enabled
8 1 enabled (DRSS) enabled enabled
9 0 disabled disabled disabled
10 1 disabled disabled disabled
11 0 disabled disabled enabled
12 1 disabled disabled enabled
13 0 disabled enabled disabled
14 1 disabled enabled disabled
15 0 disabled enabled enabled
16 1 disabled enabled enabled

The CFG2-pin defines the VOUT overvoltage protection level and if the device uses the internal clock generator or an external clock applied at the SYNCIN-pin. The CFG2-pin configures as well if the device is a single device or part of a dual device configuration, the SYNCIN and SYNCOUT-pin is enabled/disabled accordingly. During clock synchronization, the clock dither function is disabled.

OVP bit 1: OVP bit 1 and 0 set the VOUT overvoltage protection level. [00] = 64V, [01] = 50V, [10]= 35V or [11] = 28.5V.
Single: Device is used standalone using the internal oscillator.
Single ext. clock: Device is used standalone using the internal clock and synchronizes to an external clock if applied.
Primary: Device is used as primary device acting as a controller in a dual device configuration using the internal oscillator. The phase shift of the 2nd phase is either optimized for 3-phase (240° shift to 1st phase) or 4-phase (180° shift to 1st phase) operation.
Primary ext. clock: Device is used as primary device acting as a controller in a dual device configuration using the internal clock and synchronizes to an external clock if applied. The phase shift is either optimized for 3-phase (240° shift to 1st phase) or 4-phase (180° shift to 1st phase) operation.
Secondary: Device is used as secondary device using the clock provided by the primary device.
Phase shift of the device 2nd phase: Phase shift for the 2nd phase of the single, primary or secondary device as configured in the Single / Dualchip column.
SYNCIN: Defines if the clock syncing function at the SYNCIN-pin is active (on) or disabled (off). The device is only syncing to an external clock applied to the SYNCIN-pin when SYNCIN is active.
SYNCOUT: Defines if the SYNCOUT-pin is active (on) or disabled (off). A clock is only generated at the SYNCOUT-pin when SYNCOUT is active. The clock generation at the SYNCOUT-pin is disabled to save power when SYNCOUT is off.
SYNCOUT phase shift: Sets the phase shift of the SYNCOUT signal.
Clock Dithering: In case the internal oscillator is used the clock dithering is set according to the CFG1-pin setting Clock Dithering Mode. When external clock is selected the clock dithering function is disabled ignoring the CFG1-pin setting.
Table 6-4 CFG2-pin Settings
Level OVP Bit 1 Single / Dualchip Phase Shift of the Device 2nd Phase SYNCIN SYNCOUT SYNCOUT Phase Shift Clock Dithering
1 0 Single 180° off off off CFG1-pin
2 1
3 0
4 1 Single ext. clock 180° on off off disabled
5 0
6 1
7 0 Primary 3-phase 240° off on 120° CFG1-pin
8 1
9 0 Primary 4-phase 180° off on 90° CFG1-pin
10 1
11 0 Primary ext. clock 3-phase 240° on on 120° disabled
12 1
13 0 Primary ext. clock 4-phase 180° on on 90° disabled
14 1
15 0 Secondary 180° on off off disabled
16 1