SLVSIM9 September   2025 LM5125A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG0-pin, CFG1-pin, CFG2-pin)
      2. 6.3.2  Device and Phase Enable/Disable (UVLO/EN, EN2)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSP1, CSP2, CSN1, CSN2)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP1, CSP2, CSN1, CSN2)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LOx, HOx, HBx-pin)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
      2. 7.1.2 Non-synchronous Application
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Determine the Total Phase Number
        2. 7.2.2.2  Determining the Duty Cycle
        3. 7.2.2.3  Timing Resistor RT
        4. 7.2.2.4  Inductor Selection Lm
        5. 7.2.2.5  Current Sense Resistor Rcs
        6. 7.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 7.2.2.7  Low-Side Power Switch QL
        8. 7.2.2.8  High-Side Power Switch QH
        9. 7.2.2.9  Snubber Components
        10. 7.2.2.10 Vout Programming
        11. 7.2.2.11 Input Current Limit (ILIM/IMON)
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 Soft Start
        14. 7.2.2.14 CFG Settings
        15. 7.2.2.15 Output Capacitor Cout
        16. 7.2.2.16 Input Capacitor Cin
        17. 7.2.2.17 Bootstrap Capacitor
        18. 7.2.2.18 VCC Capacitor CVCC
        19. 7.2.2.19 BIAS Capacitor
        20. 7.2.2.20 VOUT Capacitor
        21. 7.2.2.21 Loop Compensation
      3. 7.2.3 Application Curves
        1. 7.2.3.1 Efficiency
        2. 7.2.3.2 Steady State Waveforms
        3. 7.2.3.3 Step Load Response
        4. 7.2.3.4 Sync Operation
        5. 7.2.3.5 AC Loop Response Curve
        6. 7.2.3.6 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 LM5125A-Q1 RHB Package, 32-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
DLY 1 O Average input current limit delay setting pin. A capacitor from DLY to AGND sets the delay from when VIMON reaches 1V until the average input current limit is enabled.
SS 2 O Soft start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. The device forces diode emulation during soft start time.
COMP 3 O Output of the internal transconductance error amplifier. Connect the loop compensation components between the pin and AGND.
AGND 4 G Analog ground pin. Connect to the analog ground plane through a wide and short path.
CSN1 5 I Current sense amplifier input of phase 1. The pin operates as the negative input pin.
CSP1 6 I Current sense amplifier input of phase 1. The pin operates as the positive input pin. Supply for the internal VI undervoltage lockout circuit.
VOUT 7 P Output voltage sensing pin. An internal feedback resistor voltage divider is connected from the pin to AGND. Connect a 0.1μF local VOUT capacitor from the pin to ground.
HO1 8 O High-side gate driver output for phase 1. Connect to the gate of the high-side N-channel MOSFET through a short, low inductance path.
HB1 9 P High-side driver supply for bootstrap gate drive for phase 1. Boot diode is internally connected from VCC to this pin. Connect a 0.1μF capacitor between the pin and SW1.
SW1 10 I Switching node connection for phase 1. Connect directly to the source of the phase 1 high-side N-channel MOSFET.
LO1 11 O Low-side gate driver output for phase 1. Connect to the gate of the low-side N-channel MOSFET through a short, low inductance path.
VCC 12 P Output of the internal VCC regulator and supply voltage input of the internal MOSFET drivers. Connect a 10μF capacitor between the pin and PGND.
PGND 13 G Power ground connection pin for low-side gate drivers and VCC bias supply.
LO2 14 O Low-side gate driver output for phase 2. Connect to the gate of the low-side N-channel MOSFET through a short, low inductance path.
SW2 15 I Switching node connection for phase 2. Connect directly to the source of the phase 2 high-side N-channel MOSFET.
HB2 16 P High-side driver supply for bootstrap gate drive for phase 2. Boot diode is internally connected from VCC to this pin. Connect a 0.1μF capacitor between the pin and SW2.
HO2 17 O High-side gate driver output for phase 2. Connect to the gate of the high-side N-channel MOSFET through a short, low inductance path.
BIAS 18 P Supply voltage input to the VCC regulator. Connect a 1μF local BIAS capacitor from the pin to ground.
UVLO/EN 19 I Undervoltage lockout programming pin. Program the converter start-up and shutdown levels by connecting this pin to the supply voltage through a resistor divider. If greater than VUVLO-RISING, phase 1 is enabled.
CSP2 20 I Current sense amplifier input of phase 2. The pin operates as the positive input pin.
CSN2 21 I Current sense amplifier input of phase 2. The pin operates as the negative input pin.
RT 22 I/O Switching frequency setting pin. The switching frequency is programmed by a resistor between the pin and AGND. Switching frequency is dynamically programmable during operation.
SYNCOUT 23 O Clock output pin. SYNCOUT provides a phase shifted clock output set by the CFG2.pin. Connect the SYNCOUT pin to ground when not used.
SYNCIN 24 I External clock synchronization pin. Input for an external clock that overrides the free-running internal oscillator. Connect the SYNCIN pin to ground when not used.
CFG2 25 I/O

Device configuration pin. Sets if the device is using the internal or external clock, if the device is used as single device or in stacked configuration and the Overvoltage Protection Level.
CFG1 26 I/O

Device configuration pin. Sets the overvoltage protection level, spread spectrum mode, PGOOD configuration and 120% peak current limit latch off.
CFG0 27 I/O

Device configuration pin. Sets the dead time and enables the 20μA ATRK current.
PGOOD 28 O

Power-good indicator with open-drain output stage. The pin is pulled low when the output voltage is less than the undervoltage threshold or great than the overvoltage threshold based on the CFG1-pin setting. The pin is also pulled low indicating faults (see Power-Good Indicator (PGOOD-pin)). Connet the pin to AGND or leave the pin floating if not in use.
MODE 29 I Operation mode selection pin selecting DEM or FPWM.
EN2 30 I Enable pin for phase 2.
ILIM/IMON 31 O Input current monitor and average input current limit setting pin. Sources a current proportional to phase 1 and phase 2 differential current sense voltage. A resistor is connected from this pin to AGND.
ATRK/DTRK 32 I Output regulation target programming pin. Program the output voltage regulation target by connecting the pin through a resistor to AGND, or by controlling the pin voltage directly with a voltage in the recommended operating range of the pin from 0.2V to 2.0V. A digital PWM signal between 8% to 80% duty cycle is automatically detected at startup and enables the digital output voltage regulation, which programs VOUT in the recommended operating range.
EP - G Exposed pad of the package. Connect the exposed pad to AGND and solder it to a large ground plane to reduce thermal resistance.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.