SLVSIZ2 April 2026 FAN31790
PRODUCTION DATA
Global Configuration Register is shown in Figure 8-1 and described in Table 8-2.
Return to the Register Map.
Register to control register actions|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|
|
RUN / Standby |
Reset |
Bus Timeout |
RESERVED |
OSC |
I2C Watchdog |
I2C Watchdog Status |
|
|
R/W-0h |
R/W-0h |
R/W-0h |
R/W-0h |
R/W-0h |
R/W-0h |
R/W-0h |
|
|
Bit |
Field |
Type |
Reset |
Description |
|---|---|---|---|---|
|
7 |
RUN/Standby |
R/W |
0b |
Places device in standby mode. Entering standby mode sets all PWM duty cycles to 0 and stops fan failure detection. However, driving the FULL_SPEED input low forces all enabled PWMOUT outputs high (100% duty cycle) regardless of the state of the Run bit. 0h = Run 0h = Standby |
|
6 |
Reset |
R/W |
0b |
Resets fan controller. This bit automatically resets itself and always returns a 0 when read. 0h = Normal operation 1h = Reset all registers to POR value |
|
5 |
Bus Timeout |
R/W |
0b |
I2C bus timeout. The I2C interface resets if SDA is low for more than 35ms 0h = Enabled 1h = Disabled |
|
4 |
RESERVED |
R/W |
0b |
|
|
3 |
OSC |
R/W |
0b |
Selects oscillator Source between the built in oscillator or external 32.768kHz crystal/ceramic resonator. Used for TACH count and sourcing the CLKOUT pin. Use crystal or ceramic resonator if higher accuracy is required. When switching from the internal oscillator to an external crystal, the device operates from the internal oscillator until the crystal oscillator has started up. If the crystal is damaged or the oscillator fails to start, the device continues to operate from the internal oscillator. 0h = Internal oscillator (default at power-on) 1h = External 32.768kHz crystal |
|
2-1 |
I2C Watchdog |
R/W |
WD_START pin |
Watchdog configuratation. When enabled, WDT is restarted by valid I2C Transactions. If there are not valid transactions between the host and the fan controller withing the watchdog period, all fan PWMs outputs will go to 100%. If a valid I2C transaction happens after a WDT timeout, the fan controller returns to it's previous configuration. Make sure the host communicates with the fan controller periodically to avoid WDT intervention. Watchdog behavor at power up is controlled by the WD_START pin. 00h = Disabled (default if WD_START = GND) 01h = 5s timeout period 10h = 10s timeout period 11h = 30s timeout period (default if WD_START = VCC) |
|
0 |
I2C Watchdog Status |
R/W |
0b |
Current status of the Watchdog Timer. Clear this bit by writing a 0 to it. 0h = Watchdog not active / I2C transactions have occurred within the watchdog period. 1h = Watchdog triggered. Time between I2C transactions has been exceeded. |
PWM Frequency Register is shown in Figure 8-2 and described in Table 8-3.
Return to the Register Map.
Register to control the bridge| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
|
PWM4-PWM6 Frequency |
PWM1-PWM3 Frequency |
||||||
| R/W - xxxx b |
R/W - xxxx b |
||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
|
7-4 |
PWM4-PWM6 Frequency |
R/W |
FREQ_START |
PWM4-PWM6 Frequency: 0000b = 25Hz 0001b = 30Hz (FREQ_START = GND) 0010b = 35Hz 0011b = 100Hz 0100b = 125Hz 0101b = 149.7Hz 0110b = 1.25kHz 0111b = 1.47kHz (FREQ_START = Floating) 1000b = 3.57kHz 1001b = 5kHz 1010b = 12.5kHz 1011b = 25kHz (FREQ_START = VCC) |
|
3-0 |
PWM1-PWM3 Frequency |
R/W | FREQ_START |
PWM1-PWM3 Frequency: 0000b = 25Hz 0001b = 30Hz (FREQ_START = GND) 0010b = 35Hz 0011b = 100Hz 0100b = 125Hz 0101b = 149.7Hz 0110b = 1.25kHz 0111b = 1.47kHz (FREQ_START = Floating) 1000b = 3.57kHz 1001b = 5kHz 1010b = 12.5kHz 1011b = 25kHz (FREQ_START = VCC) |
Fan X Configuration Register is shown in Figure 8-3 and described in Table 8-4.
Return to the Register Map.
Register duplicated to configure each of the 1-6 Fans|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|
|
Mode |
Spin-up |
Control/Monitor |
TACH Input Enable |
TACH/Locked Rotor Polarity |
Locked Rotor Polarity |
PWM/TACH |
|
|
R/W-0b |
R/W-xxb |
R/W-0b |
R/W-0b |
R/W-0b |
R/W-0b |
R/W-0b |
|
|
Bit |
Field |
Type |
Reset |
Description |
|---|---|---|---|---|
|
7 |
Mode |
R/W |
0b |
Selects either PWM or RPM Mode. PWM Duty cycle is set by the value in the associated PWMOUT Target Duty Cycle register. In RPM mode, the PWM Duty cycle is adjusted to produce the TACH count value in the associated TACH Target Count Register. When changing from PWM to RPM mode, if the current RPM value is different from the value selected in the TACH Target Count register, the PWM duty cycle starts from the current value and increment/decrements toward the desired value at the selected duty cycle rate-of-change. 0 = PWM Mode 1 = RPM Mode |
|
6-5 |
Spin-up |
R/W |
SPIN_START pin |
Spin-up is when a fan is first started, it's PWM duty cycle goes to 100% for a selectable period or time or until 2 TACH pulses have been detected. This is to help the fan get through it's initial start-up phase. After Spin-up, the duty cycle goes to the value in the PWMOUT Target Duty Cycle register. The Reset state for Spin-up is set at power-up by the state of the SPIN_START pin. 00b = No Spin-up (SPIN_START = GND) 01b = 2 TACH counts or 0.5s (SPIN_START = Unconnected) 10b = 2 TACH counts or 1s (SPIN_START = VCC) 11b = 2 TACH counts or 2s |
|
4 |
Control/Monitor |
R/W |
0b |
0 = Control fan speed 1 = Monitor only. Associated duty cycle = 0% regardless of other settings; monitor associated TACH or locked rotor if enabled by bit 3. |
|
3 |
TACH Input Enable |
R/W |
0b |
Enables associated TACH input function and fan fault detection (automatically enabled in RPM mode). When disabled and TACH input is not used, bits 1 and 2 are ignored. 0 = Disabled 1 = Enabled |
|
2 |
TACH/Locked Rotor Polarity |
R/W |
0b |
Selects TACH input function as TACH count or locked rotor. In locked rotor mode, assertion of the associated TACH input indicates that the fan has stopped. 0 = TACH 1 = Locked Rotor |
|
1 |
Locked Rotor Polarity |
R/W |
0b |
Associated TACH input either low or high in locked rotor mode indicates fan is stopped. 0 = Low 1 = High |
|
0 |
PWM/TACH Mode |
R/W |
0b |
Chooses between PWM and TACH modes. In PWM mode, associated PWMOUT produces a PWM waveform for control of fan speeds. In TACH mode, associated PWMOUT becomes a TACH input whose channel number is equal to the number of the PWMOUT channel plus six. 0 = PWM 1 = TACH |
Fan X Dynamics Register is shown in Figure 8-4 and described in Table 8-9.
Return to the Register Map.
Register to configure the fan speed control, such as PWM rate of change and time period for TACH measurements. The tables bellow describe in detail the functionality of the Table 8-6 and Table 8-7 bits:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| Speed Range | PWM Rate-of-change | Asymmetric Rate of Change | Reserved | ||||
| R-010b | R/W-011b | R/W-0b | R/W-0b | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
7-5 | Speed Range | R/W | 010b | The device determines fan speed by counting the number of internal 8192Hz (fTOSC/4) clock cycles (using an 11-bit counter) during one or more fan tachometer periods. Three bits set the nominal RPM range for the fan, as shown in the table below. For example, a setting of 010b causes the device to count the number of 8192Hz (fTOSC/4) clock cycles that occur during four complete tachometer periods. If the fan has a nominal speed of 2000 RPM and two tachometer pulses per revolution, one tachometer period is nominally 15ms, and four tachometer periods are 60ms. With an 8192Hz (fTOSC/4) clock, the TACH count is therefore equal to 491. With a fan speed of 1/3 the nominal value, the count is 1474. If the fan’s nominal speed is 1000 RPM, the fullspeed TACH count is 983. At 1/3 the nominal speed, there are 2948 clock cycles in four tachometer periods. This is greater than the maximum 11-bit count of 2047, so four tachometer periods is too many for this fan; a setting of 001 (two clock cycles) is recommended instead. The table below shows the full-speed tachometer counts for several combinations of nominal fan speeds and bits 7:5 settings. The shaded combinations provide the best results. Nonshaded combinations should generally be avoided. When setting bits 7:5, the goal is to obtain the highest tachometer count without exceeding the maximum count of 2047 when the fan is at the minimum speed of interest. For example, if the minimum speed of interest is 1/3 of full speed, the maximum tachometer count is three times the value shown in the table. |
4-2 | PWM Rate-of-Change | R/W | 011b | Sets the PWM Duty cycle rate of change. The PWM duty cycle at the associated PWMOUT outputs varies from 0 to full scale in 512 increments. The rate-of-change bits determine the time interval between duty cycle output increments/decrements. Regardless of the settings, there are a few cases for which the rate-of-change is always 0: In RPM mode, when a TACH target count of 2047 (7FFh) is selected, the duty cycle immediately goes to 0%. A full-scale target count is assumed to mean that the intent is to shut down the fan, and going directly to 0% avoids the possibility of loss of control-loop feedback at high TACH counts. If a slow-speed decrease toward 0% is desired, select a TACH target count at the slowest practical value for the fan. Once that count has been reached, selecting a count of 2047 (7FF) then takes the drive immediately to 0%. In PWM mode, when a target duty cycle of 0% is selected, the duty cycle goes to 0%. Again, it is assumed that the intent is to shut down the fan. If a slow-speed decrease toward 0% is desired, a target duty cycle of the slowest practical value for the fan in question should be chosen. Once that duty cycle has been reached, selecting a target value of 0% then takes the drive immediately to 0%. When the current duty cycle is 0% in PWM mode, selecting a new target duty cycle immediately takes the duty cycle to that value. The fan spins up first if spin-up is enabled. When the current duty cycle is 0% in RPM mode, selecting a new TACH target count that is less than 2047 (7FFh) immediately takes the duty cycle to the value in the PWMOUT Target Duty Cycle register. From this value, the duty cycle increments as needed to achieve the desired TACH target count. The fan spins up first if spin-up is enabled. |
1 | Asymmetric Rate of Change | R/W | 0h | 0 = Same rate of change whether duty cycle is increasing or decreasing. 1 = Rate of change when duty cycle is decreasing is half the rate when increasing. |
0 | Reserved | R/W | 0h | RESERVED |
BITS 7:5 | NUMBER OF TACH PERIODS COUNTED | RPM | |||||
|---|---|---|---|---|---|---|---|
500 | 1000 | 2000 | 4000 | 8000 | 16000 | ||
000b | 1 | 491 (60ms) | 245 (30ms) | 122 (15ms) | 61 (7.5ms) | 30 (3.75ms) | 15 (1.87ms) |
001b | 2 | 983 (120ms) | 491 (60ms) | 245 (30ms) | 122 (15ms) | 61 (7.5ms) | 30 (3.75ms) |
010b (default) | 4 | 1966 (240ms) | 983 (120ms) | 491 (60ms) | 245 (30ms) | 122 (15ms) | 61 (7.5ms) |
011b | 8 | 2047 (480ms) | 1966 (240ms) | 983 (120ms) | 491 (60ms) | 245 (30ms) | 122 (15ms) |
100b | 16 | 2047 (960ms) | 2047 (480ms) | 1966 (240ms) | 983 (120ms) | 491 (60ms) | 245 (30ms) |
101b, 110b, 111b | 32 | 2047 (1920ms) | 2047 (960ms) | 2047 (480ms) | 1966 (240ms) | 983 (120ms) | 491 (60ms) |
BITS 4:2 | TIME BETWEEN DUTY CYCLE INCREMENTS (ms) RPM | TIME FROM 33% TO 100% (s) | ||
|---|---|---|---|---|
PWM | RPM | PWM | RPM | |
000b | 0 | 0.9765 | 0 | 0.33 |
001b | 1.95 | 0.67 | ||
010b | 3.91 | 1.34 | ||
011b (default) | 7.81 | 2.7 | ||
100b | 15.63 | 5.3 | ||
101b | 31.25 | 10.7 | ||
110b | 62.50 | 21.4 | ||
111b | 125.00 | 42.8 | ||
User Byte Register is shown in Figure 8-5 and described in Table 8-8.
Return to the Register Map.
User can use this register for their own purposes.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
General-purpose bits | |||||||
| R/W-0000 0000b | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
7-0 | General-purpose bits | R/W | 00000000b | Volatile. These bits have no effect on the device operation |