SLVUBY7A October   2020  – October 2022 DRA821U , LP8764-Q1 , TPS6594-Q1

 

  1.   User's Guide for Powering DRA821 with TPS6594-Q1 and LP8764-Q1
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE, MCU, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8Additional Resources
  11. 9Revision History

5.4 LDO Settings

These settings detail the default voltages, configurations, and monitoring of the LDO rails. All these settings can be changed though I2C after startup. Note that only TPS6594141B-Q1 device contains LDO outputs.

Table 5-5 LDO NVM Settings
Register Name Field Name TPS6594141B-Q1
Value Description
LDO1_CTRL LDO1_EN(1) 0x0 Disabled; LDO1 regulator.
LDO1_PLDN 0x2 250 Ohm
LDO1_VMON_EN(1) 0x0 Disable OV and UV comparators.
LDO1_RV_SEL 0x1 Enabled
LDO2_CTRL LDO2_EN(1) 0x0 Disabled; LDO2 regulator.
LDO2_PLDN 0x1 125 Ohm
LDO2_VMON_EN(1) 0x0 Disabled; OV and UV comparators.
LDO2_RV_SEL 0x1 Enabled
LDO3_CTRL LDO3_EN(1) 0x0 Disabled; LDO3 regulator.
LDO3_PLDN 0x1 125 Ohm
LDO3_VMON_EN(1) 0x0 Disabled; OV and UV comparators.
LDO3_RV_SEL 0x1 Enabled
LDO4_CTRL LDO4_EN(1) 0x0 Disabled; LDO4 regulator.
LDO4_PLDN 0x1 125 Ohm
LDO4_VMON_EN(1) 0x0 Disabled; OV and UV comparators.
LDO4_RV_SEL 0x1 Enabled
LDO1_VOUT LDO1_VSET 0x1c 1.80 V
LDO1_BYPASS 0x0 Linear regulator mode.
LDO2_VOUT LDO2_VSET 0x8 0.80 V
LDO2_BYPASS 0x0 Linear regulator mode.
LDO3_VOUT LDO3_VSET 0x8 0.80 V
LDO3_BYPASS 0x0 Linear regulator mode.
LDO4_VOUT LDO4_VSET 0x38 1.800 V
LDO1_PG_WINDOW LDO1_OV_THR 0x2 +4% / +40 mV
LDO1_UV_THR 0x2 -4% / -40 mV
LDO2_PG_WINDOW LDO2_OV_THR 0x2 +4% / +40 mV
LDO2_UV_THR 0x2 -4% / -40 mV
LDO3_PG_WINDOW LDO3_OV_THR 0x2 +4% / +40 mV
LDO3_UV_THR 0x2 -4% / -40 mV
LDO4_PG_WINDOW LDO4_OV_THR 0x2 +4% / +40 mV
LDO4_UV_THR 0x2 -4% / -40 mV
(1) Note that this NVM default value can change when the device transitions to ACTIVE mode.