SLVUBY7A October   2020  – October 2022 DRA821U , LP8764-Q1 , TPS6594-Q1

 

  1.   User's Guide for Powering DRA821 with TPS6594-Q1 and LP8764-Q1
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE, MCU, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8Additional Resources
  11. 9Revision History

6.1 Configured States

In this PDN, the following four power states are configured into the PMIC devices:

  • Standby
  • Active
  • MCU Only
  • PWR SoC Error
  • Retention (both DDR and GPIO retention modes)

In Figure 6-1, the configured power states are described, along with the transition conditions required to move between configured states. Additionally, the transitions to hardware states, such as SAFE RECOVERY are described.

Figure 6-1 Pre-Configurable State Machine (PFSM) States and Transitions

The definition for each power state is described below:

    STANDBYThe PMICs are powered by a valid supply on the system power rail (VCCA > VCCA_UV) and waiting for a start-up event or condition. All device resources are powered down in the STANDBY state. EN_DRV is forced low in this state. The processor is in the Off State, no voltage domains are energized. Refer to the Section 6.3.2 sequence description. The STANDBY state is also entered when an error occurs and the PMIC transitions out of the PFSM mission states and into the FSM states. When the device returns from the FSM state the to PFSM the first state is represented by STANDBY with all of the resources powered down and EN_DRV forced low. The sequence Section 6.3.1 is performed before the PMIC leaves the PFSM and enter the FSM state SAFE_RECOVERY.
    ACTIVEThe PMICs are powered by a valid supply and have received a start-up event. The PMICs have full capacity to supply the processor and other platform modules. The processor has completed a recommended power up sequence with all voltage domains energized in both MCU & Main processor sections. MCU can now set the ENABLE_DRV bit high. Refer to the Section 6.3.8 sequence description.
    MCU ONLYThe PMICs are powered by a valid supply. Only the power resources assigned to the MCU Safety Island are on. If a given resource is maintained active, then all linked subsystems are automatically maintained active. ENABLE_DRV bit can be set high by the MCU, or remains unchanged in this state. Refer to the Section 6.3.7 sequence description.
    Pwr SoC Error The PMICs are powered by a valid supply. Only the power resources assigned to the MCU Safety Island are on. Refer to the Section 6.3.5 sequence description. The only active trigger is 'B', requiring the PMICs to return to the MCU_ONLY mode. The return to MCU_ONLY mode and eventually ACTIVE mode is only recommended after the interrupts which caused the SOC_PWR_ERROR have been cleared.
    RETENTION (DDR or GPIO)The PMICs are powered by a valid supply. Only the power resources assigned to the retention rails are on or in LPM depending on the specific resource setting. If a given resource is maintained active, then all linked subsystems are automatically maintained active. ENABLE_DRV bit is cleared by the device in this state. If the I2C_6 bit is set high in both PMICs, they enter GPIO retention state. If the I2C_7 bit is set high in both PMICs, they enter DDR retention state. These bits need to be set by I2C before a trigger for the retention state occurs. Refer to the Section 6.3.9 sequence description.