SLVUC05A November   2020  – July 2022 TPS25750

 

  1.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  2. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and Field Notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
      2. 1.3.2 Unique Address Interface Registers
  3. 2Unique Address Interface Register Detailed Descriptions
    1. 2.1  0x03 MODE Register
    2. 2.2  0x0D DEVICE_CAPABILITIES Register
    3. 2.3  0x14 - 0x19 INT_EVENT, INT_MASK, INT_CLEAR Registers
    4. 2.4  0x1A STATUS Register
    5. 2.5  0x26 POWER_PATH_STATUS Register
    6. 2.6  0x29 PORT_CONTROL Register
    7. 2.7  0x2D BOOT_STATUS Register
    8. 2.8  0x30 RX_SOURCE_CAPS Register
    9. 2.9  0x31 RX_SINK_CAPS Register
    10. 2.10 0x32 TX_SOURCE_CAPS Register
    11. 2.11 0x33 TX_SINK_CAPS Register
    12. 2.12 0x34 ACTIVE_CONTRACT_PDO Register
    13. 2.13 0x35 ACTIVE_CONTRACT_RDO Register
    14. 2.14 0x3F POWER_STATUS Register
    15. 2.15 0x40 PD_STATUS Register
    16. 2.16 GPIO Events
    17. 2.17 0x69 TYPEC_STATE Register
    18. 2.18 0x70 SLEEP_CONFIG Register
    19. 2.19 0x72 GPIO_STATUS Register
  4. 34CC Task Detailed Descriptions
    1. 3.1 Overview
    2. 3.2 PD Message Tasks
      1. 3.2.1 'SWSk' - PD PR_Swap to Sink
      2. 3.2.2 'SWSr' - PD PR_Swap to Source
      3. 3.2.3 'SWDF' - PD DR_Swap to DFP
      4. 3.2.4 'SWUF' - PD DR_Swap to UFP
      5. 3.2.5 'GSkC' - PD Get Sink Capabilities
      6. 3.2.6 'GSrC' - PD Get Source Capabilities
      7. 3.2.7 'SSrC' - PD Send Source Capabilities
    3. 3.3 Patch Bundle Update Tasks
      1. 3.3.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 3.3.2 'PBMc' - Patch Burst Mode Download Complete
      3. 3.3.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 3.3.4 Patch Burst Mode Example
      5. 3.3.5 'GO2P' - Go to Patch Mode
    4. 3.4 System Tasks
      1. 3.4.1 'DBfg' - Clear Dead Battery Flag
      2. 3.4.2 'I2Cr' - I2C Read Transaction
      3. 3.4.3 'I2Cw' - I2C Write Transaction
  5. 4User Reference
    1. 4.1 PD Controller Application Customization
    2. 4.2 Loading a Patch Bundle
  6. 5Revision History

2.10 0x32 TX_SOURCE_CAPS Register

The PD controller will transmit Source Capabilities that are written to this register without verifying them (besides limiting current see below). The user is responsible to write this register correctly per the USB PD requirements. The PD controller will only use the first TXSourceNumPDOs PDO's, the host may write multiple PDO's during configuration then dynamically write TXSourceNumPDOs to change which PDO's are advertised. If this register is changed, the host must subsequently issue the 4CC command 'SSrC'. This will cause the PD controller to re-load this TX Source Capabilities register.

The PD controller will read the capabilities of the cable and limit the maximum current in each PDO to respect the cable's VBUS Current Handling Capability.

Table 2-20 0x32 TX_SOURCE_CAPS Register
AddressNameAccessLengthUnique Per PortPower-Up Default
0x32TX_SOURCE_CAPSRW31yesInitialized by Application Configuration
Table 2-21 0x32 TX_SOURCE_CAPS Register Bit Field Definitions
BitsNameDescription
Bytes 28-31: PDO #7 (treated as a 32-bit little endian value)
31:0TXSourcePDO7Seventh Source Capabilities PDO contents. See Table 2-23.
Bytes 24-27: PDO #6 (treated as a 32-bit little endian value)
31:0TXSourcePDO6Sixth Source Capabilities PDO contents. See Table 2-23.
Bytes 20-23: PDO #5 (treated as a 32-bit little endian value)
31:0TXSourcePDO5Fifth Source Capabilities PDO contents. See Table 2-23.
Bytes 16-19: PDO #4 (treated as a 32-bit little endian value)
31:0TXSourcePDO4Fourth Source Capabilities PDO contents. See Table 2-23.
Bytes 12-15: PDO #3 (treated as a 32-bit little endian value)
31:0TXSourcePDO3Third Source Capabilities PDO contents. See Table 2-23.
Bytes 8-11: PDO #2 (treated as a 32-bit little endian value)
31:0TXSourcePDO2Second Source Capabilities PDO contents. See Table 2-23.
Bytes 4-7: PDO #1 (treated as a 32-bit little endian value)
31:0TXSourcePDO1First Source Capabilities PDO contents. See Table 2-22.
Bytes 2-3: Power path configuration for each PDO.
15:14Reserved
13:12PowerPathForPDO7Configures which PP to use for PDO7. Same format as PowerPathForPDO2.
11:10PowerPathForPDO6Configures which PP to use for PDO6. Same format as PowerPathForPDO2.
9:8PowerPathForPDO5Configures which PP to use for PDO5. Same format as PowerPathForPDO2.
7:6PowerPathForPDO4Configures which PP to use for PDO4. Same format as PowerPathForPDO2.
5:4PowerPathForPDO3Configures which PP to use for PDO3. Same format as PowerPathForPDO2.
3:2PowerPathForPDO2Configures which PP to use for PDO2.
00bReserved\.
01bReserved.
10b PP_EXT1 is used for this PDO.
1:0PowerPathForPDO1Configures which PP to use for PDO1.
00bPP_5V1 is used for this PDO.
10b PP_EXT1 is used for this PDO.
Byte 1: Header
7:3Reserved
2:0numValidPDOsNumber of valid PDOs in this register. Each PDO is 4 bytes (max of 7).

The PDO's in this register follow the definition in the USB PD specification. It is reproduced here for convenience, but for more details on each field refer to the USB PD specification.

Table 2-22 First PDO
Bits(s)Description
31:30Supply Type, this shall always be set to 00b (Fixed Supply).
29Dual-Role Power, this is overridden by the logical OR of the ProcessSwapToSink, ProcessSwapToSource, InitiateSwapToSink, and InitiateSwapToSource fields in the PORT_CONTRL register.
28USB Suspend Supported.
27:26 Reserved
25Dual-Role Data, this is overridden by the logical OR of the ProcessSwapToUFP, ProcessSwapToDFP, InitiateSwapToUFP, and InitiateSwapToDFP fields in the PORT_CONTRL register.
24Unchunked Extended Messages supported.
23:22Reserved.
21:20Peak Current.
19:10Voltage.
9:0Maximum Current.
Table 2-23 Other PDO's.
Bits(s)Description
Fixed SupplyVariable SupplyBattery Supply
31:3000b01b10b
29:20Reserved.Maximum VoltageMaximum Voltage
19:10VoltageMinimum VoltageMinimum Voltage
9:0Maximum CurrentMaximum CurrentMaximum Allowable Power