SLVUC05A November   2020  – July 2022 TPS25750

 

  1.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  2. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and Field Notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
      2. 1.3.2 Unique Address Interface Registers
  3. 2Unique Address Interface Register Detailed Descriptions
    1. 2.1  0x03 MODE Register
    2. 2.2  0x0D DEVICE_CAPABILITIES Register
    3. 2.3  0x14 - 0x19 INT_EVENT, INT_MASK, INT_CLEAR Registers
    4. 2.4  0x1A STATUS Register
    5. 2.5  0x26 POWER_PATH_STATUS Register
    6. 2.6  0x29 PORT_CONTROL Register
    7. 2.7  0x2D BOOT_STATUS Register
    8. 2.8  0x30 RX_SOURCE_CAPS Register
    9. 2.9  0x31 RX_SINK_CAPS Register
    10. 2.10 0x32 TX_SOURCE_CAPS Register
    11. 2.11 0x33 TX_SINK_CAPS Register
    12. 2.12 0x34 ACTIVE_CONTRACT_PDO Register
    13. 2.13 0x35 ACTIVE_CONTRACT_RDO Register
    14. 2.14 0x3F POWER_STATUS Register
    15. 2.15 0x40 PD_STATUS Register
    16. 2.16 GPIO Events
    17. 2.17 0x69 TYPEC_STATE Register
    18. 2.18 0x70 SLEEP_CONFIG Register
    19. 2.19 0x72 GPIO_STATUS Register
  4. 34CC Task Detailed Descriptions
    1. 3.1 Overview
    2. 3.2 PD Message Tasks
      1. 3.2.1 'SWSk' - PD PR_Swap to Sink
      2. 3.2.2 'SWSr' - PD PR_Swap to Source
      3. 3.2.3 'SWDF' - PD DR_Swap to DFP
      4. 3.2.4 'SWUF' - PD DR_Swap to UFP
      5. 3.2.5 'GSkC' - PD Get Sink Capabilities
      6. 3.2.6 'GSrC' - PD Get Source Capabilities
      7. 3.2.7 'SSrC' - PD Send Source Capabilities
    3. 3.3 Patch Bundle Update Tasks
      1. 3.3.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 3.3.2 'PBMc' - Patch Burst Mode Download Complete
      3. 3.3.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 3.3.4 Patch Burst Mode Example
      5. 3.3.5 'GO2P' - Go to Patch Mode
    4. 3.4 System Tasks
      1. 3.4.1 'DBfg' - Clear Dead Battery Flag
      2. 3.4.2 'I2Cr' - I2C Read Transaction
      3. 3.4.3 'I2Cw' - I2C Write Transaction
  5. 4User Reference
    1. 4.1 PD Controller Application Customization
    2. 4.2 Loading a Patch Bundle
  6. 5Revision History

2.14 0x3F POWER_STATUS Register

Table 2-32 0x3F POWER_STATUS Register
AddressNameAccessLengthUnique Per PortPower-Up Default
0x3FPOWER_STATUSRO2yesCleared on disconnect.
Table 2-33 0x3F POWER_STATUS Register Bit Field Definitions
BitsNameDescription
15:10ReservedReserved.
9:8ChargerAdvertiseStatus(1)(2)Charger Advertise Status.
00bCharger advertise disabled or not run.
01bCharger advertisement in process.
10bCharger advertisement complete.
11bReserved.
7:4ChargerDetectStatus(1)(2)
0hCharger detection disabled or not run.
1hCharger detection in progress.
2hCharger detection complete, none detected.
3hCharger detection complete, SDP detected.
4hCharger detection complete, BC 1.2 CDP detected.
5hCharger detection complete, BC 1.2 DCP detected.
6hCharger detection complete, Divider1 DCP detected.
7hCharger detection complete, Divider2 DCP detected.
8hCharger detection complete, Divider3 DCP detected.
9hCharger detection complete, 1.2-V DCP detected.
Ah-FhReserved.
3:2TypeCCurrentThis field is redundant with PD_STATUS.CCPullUp in register 0x40 when SourceSink is 1b. This field is redundant with PORT_CONTROL.TypeCCurrent in register 0x29 when SourceSink is 0b. In the future, this redundant field may be removed. This field is intended for Type-C Sink operation. If the port is connected as source, the field is updated upon initial connection only.
00bUSB Default Current.
01b1.5 A.
10b3.0 A.
11bExplicit PD contract sets current. A PD contract was negotiated (see other PD registers for more details).
1SourceSinkSource / Sink indicator. This bit is equivalent to PresentPDRole in register 0x40. It is replicated in this register for convenience. In the future, this redundant bit may be removed.
0bConnection requests power. The PD Controller is the source.
1bConnection provides power (PD Controller as sink).
0PowerConnectionAsserted if there is a connection. This bit is asserted when PlugPresent is TRUE and ConnState is greater than 5h. So it is redundant with information from register 0x1A. It is replicated in this register for convenience. In the future this redundant bit may be removed.
0bNo connection. The rest of bits in this register are not valid.
1bConnection present. See other bits in register for more details.
(1) This feature is not supported by TPS25750_F509.04.02.
(2) This feature is not supported by TPS25750_F509.04.02.
(1) This feature is not supported by TPS25750_F509.05.02.