SLVUCA1 November   2021 TPS7H1210-SEP

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2Setup
    1. 2.1 Input/Output Connectors and Jumper Descriptions
      1. 2.1.1 J1, J4 (–)VIN
      2. 2.1.2 J6 GND
      3. 2.1.3 J2, J5 (–)VOUT
      4. 2.1.4 J7 GND
      5. 2.1.5 J3 EN
      6. 2.1.6 TP1-5 Test Points
    2. 2.2 Equipment Setup
  4. 3Operation
  5. 4Adjustable Operation
  6. 5Test Results
    1. 5.1 Enable, Disable, and Soft Start Timing
    2. 5.2 Output Load Transients
    3. 5.3 PSRR
    4. 5.4 Noise Spectral Density
  7. 6Board Layout
  8. 7Schematic and Bill of Materials

4 Adjustable Operation

The nominal output voltage for the typical LDO circuit employing the TPS7H1210-SEP is set by two external resistors, RFB_TOP and RFB_BOT, as illustrated in Figure 4-1. RFB_TOP and RFB_BOT can be calculated for any output voltage using Equation 1and Equation 2. VFB is the Vref voltage found in the device data sheet under the Electrical Characteristics and is nominally 1.182 V.

Figure 4-1 TPS7H1210-SEP LDO Schematic Showing Adjustment Resistors
Equation 1. RFB_BOT=RFB_TOPVOUTVFB-1

where

Equation 2. V O U T R F B _ T O P + R F B _ B O T ≥ 5   µ A

Once the resistor values have been calculated, the new resistors can be installed appropriately in the correct place using the PCB and schematic diagrams of Figure 6-1 through Figure 6-4 and Figure 7-1.

For additional information on adjustable operation, see the TPS7H1210-SEP data sheet (https://www.ti.com/lit/pdf/SBVS414).