SLVUD73 April   2025 TPS7H3014-SEP , TPS7H3014-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Alternate Board Configurations
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Important Usage Notes
    3. 2.3 Connector Descriptions
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Sequence UP and DOWN Thresholds
    3. 3.3 Delay Timer
    4. 3.4 Regulation Timer
    5. 3.5 Disabled Channels
    6. 3.6 Externally Induced System RESET
  8. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
  10. 6Related Documentation

3.6 Externally Induced System RESET

The following test was performed using a FET to ground the SENSE1 pin to induce a FAULT. This can be done if an external system RESET signal is desired by the user. CH3 and CH4 were disabled during this test for convenience of displaying the results. Applying 3.3V to the gate of the FET circuitry shown in the "Optional External Reset" section of the EVM Schematic induces the external RESET. If used, it is recommended to choose a FET with low leakage to minimize the error it introduces to the SENSEx ON and OFF thresholds.

TPS7H3014EVM Sequence UPFigure 3-15 Sequence UP
TPS7H3014EVM External System RESETFigure 3-16 External System RESET