SLVUDB4 September 2025
| Connector | Pins | Description | Default Connection |
|---|---|---|---|
| JP1 | 1, 2 | UVLO/EN pin connected to VIN resistor divider | Y |
| 2, 3 | UVLO/EN pin connected to BIAS | ||
| JP2 | 1, 2 | Phase 2 is turned on | Y |
| 2, 3 | Phase 2 is turned off | ||
| JP3 | 1, 2 | Set to FPWM | |
| 2, 3 | Set to DEM | Y | |
| JP4 | 1, 2 | BIAS pin connected to VIN | Y |
| JP5 | 1, 2 | RC filter from J8 connected to ATRK/DTRK pin. | Y |
| JP6 | 1, 2 | Injection signal input for bode plot measurement | Y |
| J7 | 1, 2 | DLY pin | |
| J8 | 1,2 | Input to ATRK/DTRK pin. RC filter is inserted. | |
| J9 | 1 | SYNCIN | |
| 3 | No connection | ||
| 5 | UVLO/EN to secondary EVM | ||
| 7 | EN2 to secondary EVM | ||
| 9 | PGOOD to secondary EVM | ||
| 11 | ATRK/DTRK to secondary EVM | ||
| 13 | SS to secondary EVM | ||
| 15 | COMP to secondary EVM | ||
| 17 | MODE to secondary EVM | ||
| 19 | ILIM/IMON to secondary EVM | ||
| 21 | CFG1 of secondary EVM | ||
| 23 | CFG2 of secondary EVM | ||
| 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 | GND | ||
| J10 | 1 | SYNCOUT | |
| 3 | No Connection | ||
| 5 | UVLO/EN of primary EVM | ||
| 7 | EN2 of primary EVM | ||
| 9 | PGOOD of primary EVM | ||
| 11 | ATRK/DTRK of primary EVM | ||
| 13 | SS of primary EVM | ||
| 15 | COMP of primary EVM | ||
| 17 | MODE of primary EVM | ||
| 19 | ILIM/IMON of primary EVM | ||
| 21 | CFG1 of primary EVM | ||
| 23 | CFG2 of primary EVM | ||
| 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 | GND |