SLVUDD5 July   2025 DAC39RF20

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents (Required Equipment)
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Setup Procedure
      1. 2.1.1  Installing the DAC39RF20EVM Configuration GUI Software
        1. 2.1.1.1 Installing and Setting Up Vivado™ Lab Tools
      2. 2.1.2  Connect the DAC39RF20EVM and TSW14J59EVM
      3. 2.1.3  Connect the Power Supplies to the Boards (Power Off)
      4. 2.1.4  Connect the Spectrum Analyzer to the EVM
      5. 2.1.5  Turn On the TSW14J59EVM Power and Connect to the PC
      6. 2.1.6  Turn On the DAC39RF20EVM Power Supplies and Connect to the PC
      7. 2.1.7  Turn On the Signal Generators
      8. 2.1.8  Launching the DAC39RF20EVM GUI and Programming the DAC EVM - JMODE 0 (Bypass Mode)
      9. 2.1.9  Launching the DAC39RF20EVM GUI and Programming the DAC EVM - JMODE 1 (DUC Mode)
      10. 2.1.10 Configuration Example of DAC39RF20EVM in DDS Mode
    2. 2.2 Evaluation Board Details: Analog Outputs
    3. 2.3 FMC Signal Routing
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 Trademarks

2.3 FMC Signal Routing

Table 2-3 provides the signal routing details for the DAC39RF20EVM.

All signal routing is handled by the DAC with the internal JESD crossbar feature.

This is also featured in the JESD crossbar dialogue box within the DAC39RF20EVM GUI.

Table 2-3 Signal Routing
DAC JESD Resource Inverted FMC Resource FMC Pins TSW14J59 FPGA Resource
Lane 9 Yes DP0_C2M C2, C3 Q224 MGTYTXN0
Lane 11 Yes DP1_C2M A22, A23 Q224 MGTYTXN1
Lane 15 Yes DP2_C2M A26, A27 Q224 MGTYTXN2
Lane 5 Yes DP3_C2M A30, A31 Q224 MGTYTXN3
Lane 3 DP4_C2M A34, A35 Q225 MGTYTXN0
Lane 0 Yes DP5_C2M A38, A39 Q225 MGTYTXN1
Lane 1 Yes DP6_C2M B36, B37 Q225 MGTYTXN2
Lane 2 Yes DP7_C2M B32, B33 Q225 MGTYTXN3
Lane 7 Yes DP8_C2M B28, B29 Q226 MGTYTXN0
Lane 13 Yes DP9_C2M B24, B25 Q226 MGTYTXN1
Lane 12 Yes DP10_C2M Z24, Z25 Q226 MGTYTXN2
Lane 14 Yes DP11_C2M Y26, Y27 Q226 MGTYTXN3
Lane 6 Yes DP12_C2M Z28, Z29 Q227 MGTYTXN0
Lane 4 Yes DP13_C2M Y30, Y31 Q227 MGTYTXN1
Lane 10 Yes DP20_C2M(1) Z8, Z9 Q227 MGTYTXN2
Lane 8 Yes DP21_C2M(1) Y6, Y7 Q227 MGTYTXN3
(1) DP20_C2M and DP21_C2M can be rerouted to DP14_C2M and DP15_C2M to meet VITA compliance with other FPGA boards.