SLVUDH5A September   2025  – November 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 U1: Solder Reflow
    3. 1.3 Kit Contents
    4. 1.4 Specification
    5. 1.5 Device Information
  7. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Recommended Test Equipment
    3. 2.3 External Connections for Easy Evaluation
    4. 2.4 Test Points
    5. 2.5 Oscilloscope Probes: Probing the EVM
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 PCB Layout Guidelines
    4. 3.4 PCB Layout Example
    5. 3.5 Bill of Materials (BOM)
    6.     Trademarks
  9. 4Revision History

1.5 Device Information

Figure 1-1 DHA Package, 16-Pin SSOP (Top View)
Table 1-2 Pin Configuration and Functions
Pin Type (1) Description
Name No.
ENA 1 I

Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5V recommended maximum. Can be used to program input UVLO with a resistor divider from VIN.
PG(PG) 2 O Power-Good open-drain output pin. Remains active when VVIN_UVLOP ≤ VVIN ≤ VVIN_OVLOP; VVDD_UVP ≤ VFBVDD ≤ VVDD_OVP; VVEE_UVP ≤ VFBVEE ≤ VVEE_OVP; TJ_Primary ≤ TSHUT_P_R; and TJ_secondary ≤ TSHUT_S_R. Connect a decoupling capacitor in 0402 body size for by-passing the high frequency noise. It must be next to the Power-Good pin on the same side of the PCB as the IC.
VIN 3,4 P Primary input voltage. Connect a 10µF and a parallel 0.1µF ceramic capacitor from VIN to GNDP. The 0.1µF ceramic capacitor is for by-passing the high frequency noise and must be next to the VIN and GNDP pins
GNDP 5, 6, 7, 8 G Primary-side ground connection for VIN. Place several vias to copper pours for thermal relief. See PCB Layout Example section for more details.
COMA 9 G Secondary-side analog sense reference connection for the noise sensitive analog feedback input FBVDD, and FBVEE. Connect the low-side FBVDD feedback resistor and high frequency decoupling filter capacitors close to the COMA pin and respective feedback pin FBVDD. Connect to secondary-side gate drive voltage reference, COM. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the COMA pin.
COM 10, 11 G Secondary ground. Connect to Source of power switch.
VDD 12 P Secondary-side isolated output voltage from transformer. Connect a 10µF and a parallel 0.1µF ceramic capacitor from VDD to COM. The 0.1µF ceramic capacitor is for bypassing high frequency noise and must be next to the VDD and COM pins.
BSW 13 P Internal buck-boost converter switch pin. Connect an inductor from this point to COM. Recommend a 3.3µH to 10µH chip inductor.
VEE 14 P Secondary-side isolated output voltage for negative rail. Connect a 2.2µF ceramic capacitor from VEE to COM for bypassing high frequency noise.
FBVDD 15 I Feedback (VDD – COM) output voltage sense pin and to adjust the output (VDD – COM) voltage. Connect a resistor divider from VDD to COM so that the midpoint is connected to FBVDD. The equivalent FBVDD voltage is regulated at 2.5V with the internal hysteresis control across isolation. Adding a 470pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor is needed. The 470pF ceramic capacitor for high frequency bypass must be next to the FBVDD and COMA pins on top layer or back layer connected with vias.
FBVEE 16 I Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect one feedback resistor to VEE to program the (COM – VEE) voltage from 2V and 8V. Connect a 10pF ceramic capacitor from FBVEE to COMA for bypassing high frequency noise. The 10pF ceramic capacitor must be next to the FBVEE pin on top layer or back layer connected with vias.
(1) TYPE: P=Power, PG=Primary Ground, SG=Secondary Return, SGA=Secondary Return Analog, I=Input, O=Output