SLVUDH5A September 2025 – November 2025
The PCB layout example, highlighted in the following figures, is based on the EVM schematic shown in Figure 3-1 and PCB layer images shown in Figure 3-4 to Figure 3-7.
Figure 3-8 VIN (C2, C3)
and VDD (C5, C8) Capacitors
Figure 3-9 FBVDD (R6-7,
C6), FBVEE (R5, C4), COMA Routing
Figure 3-10 Thermal
Vias
Figure 3-11 Isolation Keep
Out Region
Figure 3-12 Bottom Side,
Buck Boost, VEE LC Placement and Routing
Figure 3-13 Top Side,
Component Placement and Routing