SLWU079D March 2012 – April 2016
The TSW1405 has an LED labeled D1 Done that is lit when the FPGA is finished loading a bit file and is ready for use. An additional LED labeled D2 is normally not installed and is reserved for future use. For the initial release of the TSW1405, the LED D2 (if installed) will flash when an LVDS clock is present from the ADC EVM.