SLWU079D March   2012  – April 2016

 

  1.   TSW140x High Speed Data Capture/Pattern Generator Card
    1.     Trademarks
    2. 1 Functionality
      1. 1.1 ADC EVM Data Capture
      2. 1.2 DAC EVM Pattern Generator
    3. 2 Hardware Configuration
      1. 2.1 Power Connections
        1. 2.1.1 Output Power Regulators
      2. 2.2 Switches, Jumpers and Fuses
        1. 2.2.1 Switches and Pushbuttons
        2. 2.2.2 Jumpers
        3. 2.2.3 Fuses
      3. 2.3 LEDs
      4. 2.4 Connectors
        1. 2.4.1 Input LVDS ADC Interface Connector
        2. 2.4.2 JTAG Connector
        3. 2.4.3 Input CMOS ADC Interface Connector
        4. 2.4.4 Output LVDS Connector
        5. 2.4.5 Output CMOS DAC Interface Connector
        6. 2.4.6 USB I/O Connection
    4. 3 Software Start up
      1. 3.1 Installation Instructions
      2. 3.2 USB Interface and Drivers
      3. 3.3 Device ini Files
    5. 4 ADC Data Capture Software Operation
      1. 4.1 Testing a TSW1400 EVM with an ADS5281 EVM
      2. 4.2 Testing a TSW1400EVM with an ADS62P49EVM (CMOS Interface)
    6. 5 TSW1400 Pattern Generator Operation
      1. 5.1 Testing a TSW1400 EVM with a DAC3152 EVM
      2. 5.2 Loading DAC Firmware
      3. 5.3 Configuring TSW1400 for Pattern Generation
      4. 5.4 Testing a TSW1400 EVM with a DAC5688EVM (CMOS Interface)
    7. 6 TSW1405 Functional Description
      1. 6.1 Hardware Description
        1. 6.1.1 Power Connections
        2. 6.1.2 Pushbuttons
        3. 6.1.3 Jumpers
        4. 6.1.4 LEDs
      2. 6.2 Software Operation
        1. 6.2.1 Channel Selection
    8. 7 TSW1406 Functional Description
      1. 7.1 Hardware Description
        1. 7.1.1 Power Connections
        2. 7.1.2 Pushbuttons
        3. 7.1.3 Jumpers
        4. 7.1.4 LEDs
      2. 7.2 Software Operation
    9. 8 Revision History

2.3 LEDs

Eleven LEDs are on the TSW1400EVM to indicate the presence of power and the state of the FPGA.

The LED on the left edge of the board illuminates to indicate the presence of a 5-V power to the board after SW7 is placed in the “ON” position.

LED D1 illuminates to indicate that the FPGA programming has completed and is now operational.

USER_LED0 and LED1 indicate transmission of data samples over SPI interface.

USER_LED2 turns off when the FPGA is in reset mode.

USER_LED3 indicates the FPGA PLL1 is locked to the ADC input clock from port 0.

USER_LED4 indicates the FPGA PLL2 is locked to the ADC input clock from port 1 or locked to the FPGACLK from the DAC when in the DAC mode.

USER_LED5 indicates that the DDR memory initialization is complete and the interface is ready to use.

USER_LED6 and LED7 indicate that the two SPI FIFO’s are empty.

LED D10 indicates the presence of 6-V power to the DAC EVM interface connector J4.