6 Theoretical example: Frequency planning with decimation

Consider an interleaved ADC sampling a common RF input signal at Fs. The interleaving process introduces a spur at Fs/2-Fin, which can interfere with the intended signal. Applying a decimation-by-2 filter, as shown in Figure 4, makes it possible to attenuate this spur to levels within the decimation filter’s rejection limits. Additionally, the decimation process reduces the ADC’s output data rate, enabling cost-effective FPGA interfacing and simplifying downstream processing. Additionally, the wideband noise reduction introduces a 3dB process gain as a result of the N (that is Noise) in SNR being cut in half, while the S (that is Signal) stays the same.

Figure 4 Decimation filter response of theoretical data at 500MSPS with 70MHz FIN (with decimation factor of 2).