CDCLVC1310

ACTIVE

Universal input, 10-output low impedance LVCMOS buffer

Top

Product details

Parameters

Function Single-ended Additive RMS jitter (Typ) (fs) 25 Output frequency (Max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 1.5, 1.8, 2.5, 2.8 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Features 1:10 fanout, Level translation Operating temperature range (C) -40 to 85 Rating Catalog Output type LVCMOS Input type HCSL, LVCMOS, LVDS, LVPECL, SSTL, XTAL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RHB) 32 25 mm² 5 x 5 open-in-new Find other Clock buffers

Features

  • High-Performance Crystal Buffer With Ultralow Noise
    Floor of –169 dBc/Hz
  • Additive Phase Noise/Jitter Performance Is
    25 fsRMS (Typ.)
  • Level Translation With 3.3-V or 2.5-V Core and
    3.3-V, 2.5-V, 1.8-V, or 1.5-V Output Supply
  • Device inputs consist of primary, secondary,
    and crystal inputs, and manually selectable
    (through pins) using the input MUX. The primary
    and secondary inputs can accept LVPECL, LVDS,
    HCSL, SSTL or LVCMOS signals and crystal input.
    • Crystal Frequencies Supported Are From
      8 MHz to 50 MHz
    • Differential and Single-Ended Input Frequencies
      Supported Are up to 200 MHz
  • 10 Single-Ended LVCMOS Outputs. The outputs can
    operate at 1.5-V, 1.8-V, 2.5-V or 3.3-V
    Power-Supply Voltage.
    • LVCMOS Outputs Operate up to 200 MHz
    • Output Skew Is 30 ps (Typical)
    • Total Propagation Delay Is 2 ns (Typical)
    • Synchronous and Glitch-Free Output Enable Is
      Available
  • Offered in QFN-32 5-mm × 5-mm Package With
    Industrial Temperature Range of –40°C to 85°C
  • Can Overdrive Crystal Input With LVCMOS Signal up to 50 MHz
open-in-new Find other Clock buffers

Description

The CDCLVC1310 is a highly versatile, low-jitter, low-power clock fanout buffer which can distribute to ten low-jitter LVCMOS clock outputs from one of three inputs, whose primary and secondary inputs can feature differential or single-ended signals and crystal input. Such a buffer is good for use in a variety of mobile and wired infrastructure, data communication, computing, low-power medical imaging, and portable test and measurement applications. When the input is an illegal level, the output is at a defined state. One can set the core to 2.5 V or 3.3 V, and output to 1.5 V, 1.8 V, 2.5 V or 3.3 V. Pin programming easily configures the CDCLVC1310. The overall additive jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small 32-pin 5-mm × 5-mm QFN package.

open-in-new Find other Clock buffers
Download
Similar products you might be interested in
open-in-new Compare products
Similar but not functionally equivalent to the compared device:
CDCVF2310 ACTIVE High performance 1:10 clock buffer for general purpose applications with support up to 105C High Performance 1:10 LVCMOS Clock Buffer
LMK00101 ACTIVE Ultra-low jitter LVCMOS fanout buffer/level translator with universal input and 10 outputs Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 5
Type Title Date
* Data sheet Ten-Output Low-Jitter Low-Power Clock Buffer and Level Translator datasheet (Rev. E) Jan. 06, 2014
Technical article Timing is Everything: How to measure additive jitter Jul. 18, 2014
Application note Crystal Oscillator Performance of the CDCLVC1310 Aug. 09, 2012
Application note Phase Noise Performance of CDCLVC1310 Jan. 26, 2012
User guide 10-Output Low Jitter Low Power Differential to LVCMOS Clock Buffer - Evaluation Nov. 29, 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
149
Description

The CDCLVC1310 is a highly versatile, low jitter and low power clock fan out buffer, which distributes up to ten low jitter LVCMOS clock outputs. The clock is derived from one of three inputs, whose primary and secondary inputs feature differential or single-ended signals and the third input is a (...)

Features
  • Easy-to-use evaluation board to fan out low phase-noise clocks
  • Easy device setup
  • Fast configuration
  • Control pins configurable through jumpers
  • Board powered at 2.5-/3.3-V for VDD and at 1.5-/1.8-/2.5-/3.3-V for VDDO
  • Single-ended or differential input clocks or crystal input

Design tools & simulation

SIMULATION MODEL Download
SCAM053.ZIP (127 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
DESIGN TOOL Download
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Features
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

CAD/CAE symbols

Package Pins Download
VQFN (RHB) 32 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos