SNAA406B August   2024  – May 2025 LMK6C

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction and Test Methodology
  5. 2Simulation Setup
  6. 3Routing Topologies and Simulation Results
    1. 3.1 Single-Line
    2. 3.2 Star Line
    3. 3.3 Split Line
    4. 3.4 Star Line vs. Split Line
  7. 4Lab Measurements
    1. 4.1 Lab Measurement Setup
    2. 4.2 Lab Measurement Results and Correlation to Simulation Data
  8. 5Trace Length Mismatch Between Loads
  9. 6Application Example: FPD-Link
  10. 7Summary
  11. 8References
  12. 9Revision History

2 Simulation Setup

IBIS SI simulations were ran in MentorGraphics' Hyperlynx tool. Altium board files were exported to a free-form SI schematic, modeling the effect of transmission lines and stubs for actual PCB trace routing and layer stackup. Figure 2-1 shows a simplified simulation example with a LVCMOS clock driver, transmission line model, and load capacitance. After extracting PCB layout to an SI model, a series of transmission line models are added to the circuit to represent trace interconnects, passive component pads, stubs, and other factors impacting the trace impedance. The Hyperlynx waveform viewer allows the user to change the clock oscillation frequency along with the time and vertical scaling, similarly to a traditional oscilloscope. The probe is placed at the load capacitor rather than the driver to simulate what a receiver can detect in a real system.

Hyperlynx SI Simulation Setup Figure 2-1 Hyperlynx SI Simulation Setup