SNAA406B August   2024  – May 2025 LMK6C

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction and Test Methodology
  5. 2Simulation Setup
  6. 3Routing Topologies and Simulation Results
    1. 3.1 Single-Line
    2. 3.2 Star Line
    3. 3.3 Split Line
    4. 3.4 Star Line vs. Split Line
  7. 4Lab Measurements
    1. 4.1 Lab Measurement Setup
    2. 4.2 Lab Measurement Results and Correlation to Simulation Data
  8. 5Trace Length Mismatch Between Loads
  9. 6Application Example: FPD-Link
  10. 7Summary
  11. 8References
  12. 9Revision History

7 Summary

These simulation results and lab measurements have shown some of the factors to determine if driving multiple loads with a single LVCMOS oscillator is feasible in a system. Driving multiple loads from a single LVCMOS oscillator can always degrade signal integrity in some way. For best performance one can limit the numbers of loads which needs to be directly driven by an oscillator by using a Clock Buffer.

Guidelines for driving multiple loads with a single oscillator:

  • Limit the number of loads to 2 to minimize performance degradation in terms of reduced rise or fall time, excessive signal reflections, and reduced signal amplitude
  • Maximize common trace length before branching out to individual receivers as shown in Star Line topologies
  • Limit total receiver capacitance to achieve fast rise/fall time

These guidelines can provide a basis for driving multiple loads in your system. By reducing the number of loads, reducing the branch trace length, and reducing the total parasitic and receiver capacitance, you can minimize the negative consequences of driving multiple loads with a single oscillator in your system. The Star Line topology best models this kind of routing situation. If achieving absolute best performance is a priority, traces can never be split into multiple loads and instead a clock buffer like the 4-Channel Output LVCMOS 1.8-V Buffer can be used to fanout the clock signal and drive multiple loads.