The board layout parameters were extracted and a signal integrity simulation was ran in Hyperlynx using the same procedure described in Section 2 with a 2pF load capacitance at each output. The measurements collected with this board and a comparison with the predicted values based on simulation results are given below.

From the results shown in Table 4-1, the trace routing topology had very little impact on jitter performance. Note that jitter measurements were taken with a phase noise analyzer that contains an internal 50Ω termination, which reduces reflections measured at the receiver compared to a high-impedance, purely capacitive load. The rise/fall time trends of the simulated measurements closely correlate with the lab measurements. Trace numbering of the x-axis in Figure 4-2 corresponds to the same numbering scheme used in Table 4-1 and the labels on Figure 4-1. Simulation results become less closely coupled compared to the lab measurements as the routing fanout increases. This is mainly the result of unmodeled parasitic capacitances of the SMA adapters, cables, and probes in the test setup. Based on this correlation from lab measurements vs. simulation data, you can expect the simulation rise/fall time results to match the real measurement results within ±25% margin. This margin accounts for part-to-part variation, PCB manufacturing tolerances of the copper pour thickness affecting parasitic capacitance and characteristic trace impedance, and other environmental factors. To summarize, system designers can use IBIS simulations to confidently estimate the rise/fall time and signal integrity of clock signals for different routing schemes when driving multiple loads.

Output amplitude maintained rail-to-rail specifications in all routing topologies with a 2pF load, but can be degraded as the number of loads or total load capacitance increases. In both the simulations and real lab measurements, routing with the split near the load (star-line topology) results in better performance.