SNAA406B August   2024  – May 2025 LMK6C

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction and Test Methodology
  5. 2Simulation Setup
  6. 3Routing Topologies and Simulation Results
    1. 3.1 Single-Line
    2. 3.2 Star Line
    3. 3.3 Split Line
    4. 3.4 Star Line vs. Split Line
  7. 4Lab Measurements
    1. 4.1 Lab Measurement Setup
    2. 4.2 Lab Measurement Results and Correlation to Simulation Data
  8. 5Trace Length Mismatch Between Loads
  9. 6Application Example: FPD-Link
  10. 7Summary
  11. 8References
  12. 9Revision History

6 Application Example: FPD-Link

FPD-Link devices require an external REFCLK, typically 25MHz or 27MHz LVCMOS in most applications. For this experiment, one LVCMOS oscillator generated the REFCLK signal for two DS90UB971 serializer and US90UB9702 deserializer pairs. REFCLK was generated with a CDC6C BAW oscillator, and fanned out to the two FPD-Link SerDes pairs using trace 3 on the multi-load board (fanned out to 2 loads, 2" trace length split near the oscillator). A smaller coupon board was used to add an additional 2" of trace length, for 4" in total. SMA to 2-pin female header cables connected the multi-load board to the external REFCLK header on two DS90UB9702 EVMs.

CDC6C Providing REFCLK for 2 FPD-Link SerDes Pairs: Block Diagram Figure 6-1 CDC6C Providing REFCLK for 2 FPD-Link SerDes Pairs: Block Diagram

With both FPD-Link SerDes pairs sharing a REFCLK, link was established without any errors. An Eye Opening Margin (EOM) test was performed to make sure that each pair was generating a stable link. Both DS90UB971/9702 pairs were able to maintain link simultaneously with a shared REFCLK signal across a sweep of EQ settings. This test confirms that this can be possible for a single LVCMOS oscillator to drive multiple loads in some applications.

FPD-Link Eye Opening Margin (EOM) Result Figure 6-2 FPD-Link Eye Opening Margin (EOM) Result