SNAA406B August   2024  – May 2025 LMK6C

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction and Test Methodology
  5. 2Simulation Setup
  6. 3Routing Topologies and Simulation Results
    1. 3.1 Single-Line
    2. 3.2 Star Line
    3. 3.3 Split Line
    4. 3.4 Star Line vs. Split Line
  7. 4Lab Measurements
    1. 4.1 Lab Measurement Setup
    2. 4.2 Lab Measurement Results and Correlation to Simulation Data
  8. 5Trace Length Mismatch Between Loads
  9. 6Application Example: FPD-Link
  10. 7Summary
  11. 8References
  12. 9Revision History

1 Introduction and Test Methodology

When clocking a system at high frequencies or with long trace lengths, cables and PCB traces are usually treated as transmission lines and not just as a simple wire. As a general rule, the estimate is that transmission line effects need to be considered when the propagation delay through the trace or cable is greater than 0.25 times the signal's rise time. For example, a typical PCB made of FR-4 material can have a signal propagation delay of around 150ps/in. Assuming a signal rise time of 1ns, then any trace longer than around 1.5 inches can behave like a transmission line and can have signal integrity concerns if not addressed.

The following simulation results show the effects of driving multiple loads with a single LVCMOS oscillator using various routing schemes. To perform the simulations, we designed a 4-layered stackup in Altium Designer and determined the trace width needed to create a nominal 50Ω characteristic trace impedance. This particular stackup was chosen such that traces with a nominal 50Ω impedance can be closely matched to the pad size of 0201 passive components, resulting in minimal reflections when the signal passes through onboard resistors and capacitors.

With this stackup we designed a series of PCB layouts to emulate several different methods of routing a driver to multiple loads . The layout files were then converted for use in IBIS SI simulations using a 25MHz TI BAW Oscillator as the driver.

Stackup Used in Load Board SimulationFigure 1-1 Stackup Used in Load Board Simulation
Table 1-1 Trace Impedance vs. Thickness Using Load Board Stackup
Trace Thickness (mil)Characteristic Impedance (Z0) of Trace
960Ω
1350Ω
2040Ω

When routing to multiple loads, line resistors can be placed for 50Ω impedance matching. Each routing scheme drives either one, two, or four loads with a combined capacitance of 10pF. The overall load capacitance was constant across all test configurations to make sure that the routing topology was the only variable that was changed. Figure 1-2 demonstrates how increasing the overall capacitive load on an LVCMOS oscillator output can increase rise and fall times and can degrade performance. This factor was eliminated from the experiment by using a constant 10pF load to account for the worst case scenario of driving four loads, each with the nominal load capacitance of 2.5pF. Section 3 contains a more in-depth description of the various trace and load topologies that were tested.

LMK6C Rise or Fall time (ps) vs Temperature and Load Capacitance for 25MHz Output Frequency, 3.3V Supply Figure 1-2 LMK6C Rise or Fall time (ps) vs Temperature and Load Capacitance for 25MHz Output Frequency, 3.3V Supply