SNAS856A September   2024  – March 2025 REF80

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Heater
      2. 7.3.2 Buried Zener Reference
  9. 8 Parameter Measurement Information
    1. 8.1 Long-Term Stability
    2. 8.2 Temperature Drift
    3. 8.3 Thermal Hysteresis
    4. 8.4 Noise Performance
      1. 8.4.1 1/f Noise
      2. 8.4.2 Broadband Noise
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application: Basic Voltage Reference Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Typical Application Circuits
        1. 9.2.2.1 Precision Voltage Divider Connection
        2. 9.2.2.2 Calibration Signal
    3. 9.3 Power Supply Recommendation
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

At VDD = 10V, VHET= 30V, TSET = 115℃, CREF_Z = 10µF, CVDD = 1µF,  IL = 0mA, T-SET = Open, OP_STBL is pulled up to 5V through 10kΩ resistor,  minimum and maximum specifications across supported temperature range, typical specifications TA = 25℃; unless otherwise noted
PARAMETER TEST CONDITION MIN TYP MAX UNIT
ACCURACY AND DRIFT
REF_Z Output voltage 7.6 V
Output voltage accuracy –50 50 mV
Output voltage temperature coefficient(1) TA = 0℃ to 70℃ 0.05 0.2 ppm/℃
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability 1000 hours, TA = 25℃, TSET = 115℃ 3 ppm
1000 hours to 5000 hours , TA = 25℃, TSET = 115℃ 0.3
Output voltage hysteresis Cycle 1 1 ppm
Cycle 2 0.3 ppm
NOISE
enp-p Low frequency noise ƒ = 0.1Hz to 10Hz 0.12 ppmp-p
en Output voltage noise ƒ = 10Hz to 100Hz, 0.6 uVrms
LINE REGULATION
ΔVREF_Z/ΔVDD Line regulation VDD = 10V to 16.5V 4 10 ppm/V
POWER SUPPLY
VDD Input voltage 10 16.5 V
VHET Input voltage (HEATP - HEATM) 10 42 V
IHET Start up current 335 mA
Quiescent current TA = 25℃, TSET = 115℃, VHET = 10V 75
TA = 25℃,  TSET = 115℃,   VHEATER = 42V 18
IVDD Quiescent current 15 mA
TURNON TIME
Start-up VREF_Z  REF_Z settled within ±3ppm from VDD and VHET power up time 100 sec
Heater regulation time OP_STBL goes to logic high level form VHET power-up time 250 ms
OP_STBL
VOL Low level output voltage OP_STBL Pin Current IOL = 5mA  0.65 V
ILKG Leakage Current when output is high Pullup Voltage at OP_STBL VPULLUP = 18V 100 nA
STABLE CAPACITANCE RANGE
Input capacitor range 0.1 µF
Output capacitor range (2) 10 100 µF
(1) Temperature drift is calculated using box method
(2) ESR for the capacitor can range from 10mΩ to 400mΩ