SNIS118I July 1999 – October 2025 LM50 , LM50HV
PRODUCTION DATA
The LM50 and LM50HV devices handle capacitive loading very well. Without any special precautions, the LM50 and LM50HV can drive capacitive load up to 1μF. These devices have a nominal 2kΩ output impedance (shown in Functional Block Diagram). The temperature coefficient of the output resistors is approximately 1300ppm/°C. Taking into account this temperature coefficient and the initial tolerance of the resistors, the output impedance of the device does not exceed 4kΩ. In an extremely noisy environment adding filtering can be necessary to minimize noise pickup. TI recommends adding a CBy-pass = 0.1µF capacitor between +VS and GND to bypass the power supply noise voltage, as shown in Figure 8-3. Adding a capacitor (CLoad) from VO to ground can be necessary. A 1µF output capacitor with the 4kΩ output impedance forms a 40Hz low-pass filter. Because the thermal time constant of the LM50 and LM50HV is much slower than the 25ms time constant formed by the RC, the overall response time of the device is not significantly affected. For much larger capacitors, this additional time lag increases the overall response time of the LM50 and LM50HV.
To avoid glitch of start-up power supply (input) response especially when CBy-pass is not used (as shown in Figure 6-20, Figure 8-4 and Figure 8-5) on LM50 (new chip) and LM50HV devices, a minimum CLoad must be placed between VO and ground especially when LM50 (new chip) and LM50HV devices are utilized in the comparator circuits.
The minimum CLoad capacitor is varied over different operating temperature range and power supply ramp rate as shown in the Table 8-2. Please noted that the rise time (tr) can be translated to ramp rate of power supply (SR) by: SR (V/μs) = 0.8 × +VS (V) / tr (μs).
Load Capacitance | +VS = 3.3V | +VS = 5V | +VS = 36V | |||
|---|---|---|---|---|---|---|
| tr = 0.1μs | tr = 1μs | tr = 0.1μs | tr = 1μs | tr = 0.1μs | tr = 1μs | |
| CLoad (min) at TA = -40°C | 0.33nF | 0.33nF | 0.47nF | 0.47nF | 10nF | 10nF |
| CLoad (min) at TA = 25°C | 0.02nF | NA | 0.05nF | 0.05nF | 0.68nF | 0.68nF |
| CLoad (min) at TA = 150°C | NA | NA | NA | NA | 0.12nF | 0.12nF |
Figure 8-6 and Figure 8-7 show start-up step response to 3.3V and 36V power supply with around 3.3V/μs ramp rate (without using CBy-pass). Each figure shows the output response to no load and minimum required CLoad when glitch overshoot is eliminated. The worst-case scenario (as shown in Table 8-2) is happened when operating temperature is -40°C.