SNLA241A October   2015  – July 2025 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Factors Affecting Power Consumption
    1. 2.1 Operational Mode
    2. 2.2 I/O Pin Loading
    3. 2.3 Channel Utilization
    4. 2.4 Payload
    5. 2.5 Temperature
  6. 3Power Saving Modes
    1. 3.1 IEEE Power Down
    2. 3.2 Deep Power Down Mode
    3. 3.3 Active Sleep
    4. 3.4 Passive Sleep
  7. 4Power Consumption Baseline Data
    1. 4.1 Base Line Power Consumption
  8. 5Summary
  9. 6Appendix
    1. 6.1 1000M Power
    2. 6.2 100M Power
    3. 6.3 10M power
    4. 6.4 Channel Utilization 1000M
    5. 6.5 Power Down Consumption
  10. 7Revision History

2.2 I/O Pin Loading

Digital I/O pin loading affects the power consumption of the PHY. Digital I/O pins include clock output pins, general-purpose output pins, and MII digital output pins. For example, 6 digital outputs driving 5 pF loads at 25 MHz can result in a current demand of 15 mA in a typical application. Power demand can be reduced by making MII signal traces as short as possible, and by adding series termination to the MII output signals. Some PHYTER products include integrated digital output series resistance. For more details, see the device-specific data sheets

Higher voltage level on the Digital I/O pins also leads to higher power consumption. See Appendix Section 6.1 for observing the power variation due to change in VDDIO voltage.