SNLA241A October   2015  – July 2025 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Factors Affecting Power Consumption
    1. 2.1 Operational Mode
    2. 2.2 I/O Pin Loading
    3. 2.3 Channel Utilization
    4. 2.4 Payload
    5. 2.5 Temperature
  6. 3Power Saving Modes
    1. 3.1 IEEE Power Down
    2. 3.2 Deep Power Down Mode
    3. 3.3 Active Sleep
    4. 3.4 Passive Sleep
  7. 4Power Consumption Baseline Data
    1. 4.1 Base Line Power Consumption
  8. 5Summary
  9. 6Appendix
    1. 6.1 1000M Power
    2. 6.2 100M Power
    3. 6.3 10M power
    4. 6.4 Channel Utilization 1000M
    5. 6.5 Power Down Consumption
  10. 7Revision History

3.1 IEEE Power Down

The PHY is powered down except for essential functions. Access to the PHY via MDIO-MDC pins is retained. This mode can be activated by asserting external PWDN pin or by setting bit 11 of BMCR (Register 0x00).

The PHY can be taken out of this mode by a power cycle, software reset or by writing 0 to bit 11 in BMCR register. However, the external PWDN pin should be de-asserted. If the PWDN pin is kept asserted then the PHY will remain in power down.