SNLA241A October   2015  – July 2025 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Factors Affecting Power Consumption
    1. 2.1 Operational Mode
    2. 2.2 I/O Pin Loading
    3. 2.3 Channel Utilization
    4. 2.4 Payload
    5. 2.5 Temperature
  6. 3Power Saving Modes
    1. 3.1 IEEE Power Down
    2. 3.2 Deep Power Down Mode
    3. 3.3 Active Sleep
    4. 3.4 Passive Sleep
  7. 4Power Consumption Baseline Data
    1. 4.1 Base Line Power Consumption
  8. 5Summary
  9. 6Appendix
    1. 6.1 1000M Power
    2. 6.2 100M Power
    3. 6.3 10M power
    4. 6.4 Channel Utilization 1000M
    5. 6.5 Power Down Consumption
  10. 7Revision History

3.3 Active Sleep

In this mode all the digital and analog blocks are powered down. The PHY is automatically powered up when a link partner is detected. This mode is useful for saving power when the link partner is down/inactive but the PHY cannot be powered down. In Active Sleep mode, the PHY will still routinely send NLP to the link partner. This mode can be active by writing 1 to bit 9 and 0 to bit 8 for PHYCR (Register 0x10).