SNVSCO2 November   2025 LM51261A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration (CFG-pin)
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Dual Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Fault Indicator (nFAULT-pin)
      12. 6.3.12 Slope Compensation (CSP, CSN)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSP, CSN)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 Signal Deglitch Overview
      17. 6.3.17 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB-pin)
      18. 6.3.18 I2C Features
        1. 6.3.18.1 Register VOUT (0x0)
        2. 6.3.18.2 Register Configuration 1 (0x1)
        3. 6.3.18.3 Register Configuration 2 (0x2)
        4. 6.3.18.4 Register Configuration 3 (0x3)
        5. 6.3.18.5 Register Operation State (0x4)
        6. 6.3.18.6 Register Status Byte (0x5)
        7. 6.3.18.7 Register Clear Faults (0x6)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
    5. 6.5 Programming
      1. 6.5.1 I2C Bus Operation
  8. 7 LM51261A-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Feedback Compensation
      2. 8.1.2 3 Phase Operation
      3. 8.1.3 Non-synchronous Application
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Determine the Total Phase Number
        2. 8.2.2.2  Determining the Duty Cycle
        3. 8.2.2.3  Timing Resistor RT
        4. 8.2.2.4  Inductor Selection Lm
        5. 8.2.2.5  Current Sense Resistor Rcs
        6. 8.2.2.6  Current Sense Filter RCSFP, RCSFN, CCS
        7. 8.2.2.7  Low-Side Power Switch QL
        8. 8.2.2.8  High-Side Power Switch QH
        9. 8.2.2.9  Snubber Components
        10. 8.2.2.10 Vout Programming
        11. 8.2.2.11 Input Current Limit (ILIM/IMON)
        12. 8.2.2.12 UVLO Divider
        13. 8.2.2.13 Soft Start
        14. 8.2.2.14 CFG Settings
        15. 8.2.2.15 Output Capacitor Cout
        16. 8.2.2.16 Input Capacitor Cin
        17. 8.2.2.17 Bootstrap Capacitor
        18. 8.2.2.18 VCC Capacitor CVCC
        19. 8.2.2.19 BIAS Capacitor
        20. 8.2.2.20 VOUT Capacitor
        21. 8.2.2.21 Loop Compensation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Efficiency
        2. 8.2.3.2 Steady State Waveforms
        3. 8.2.3.3 Step Load Response
        4. 8.2.3.4 AC Loop Response Curve
        5. 8.2.3.5 Thermal Performance
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.1.2 3 Phase Operation

For higher power, LM51261A can be used in 3 phase operation together with a LM51251A device.

To configure for 3-phase interleaved operation, configure LM51251A as the primary device and configure LM51261A as a secondary device. Shown in Figure 8-2 is the 3-phase configuration with a LM51251A combined with a LM51261A device. The phase shift for phase 3 is 120 degrees.

LM51261A-Q1 3-Phase Interleaved Boost Configuration Figure 8-2 3-Phase Interleaved Boost Configuration
LM51261A-Q1 3-Phase Interleaved Boost Configuration Figure 8-3 3-Phase Interleaved Boost Configuration

The typical application schematic for 3-phase operation is shown in Figure 8-4.

LM51261A-Q1 3-phase Typical Application Schematic Figure 8-4 3-phase Typical Application Schematic

Connect Syoncout of LM51251A to SYNCIN of LM51261A. Also connect COMP, IMON,SS and mode pin of both devices together.