SNVSCQ8B November   2025  – July 2026 LM654A5-Q1 , LM654B0-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Output Voltage Selection
      2. 7.3.2  EN Pin and Use as VIN UVLO
      3. 7.3.3  Device Configuration
      4. 7.3.4  Mode Selection
        1. 7.3.4.1 MODE/SYNC Pin Uses for Synchronization
        2. 7.3.4.2 Clock Locking
      5. 7.3.5  Adjustable Switching Frequency and Phase Shift
      6. 7.3.6  Dual Random Spread Spectrum (DRSS)
      7. 7.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 7.3.8  Bootstrap Voltage (BST Pin)
      9. 7.3.9  Soft Start and Recovery From Dropout
      10. 7.3.10 Safety Features
        1. 7.3.10.1 Power-Good Monitor
        2. 7.3.10.2 Overcurrent and Short-Circuit Protection
        3. 7.3.10.3 Hiccup
        4. 7.3.10.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Peak Current Mode Operation
        2. 7.4.2.2 Auto Mode Operation
          1. 7.4.2.2.1 Diode Emulation
        3. 7.4.2.3 FPWM Mode Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Example Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Choosing the Switching Frequency
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitors
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Setting the Output Voltage
        6. 8.2.2.6 Compensation Components
        7. 8.2.2.7 Feed-forward Capacitor (CFF)
        8. 8.2.2.8 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.4.1 Layout Guidelines

The PCB layout of any DC-DC converter is critical to the optimal performance of the design. Bad PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the regulator is dependent on the PCB layout to a great extent. In a buck converter, the most EMI-critical PCB feature is the loop formed by the input capacitor or capacitors and power ground. This action is shown in Figure 8-94. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. Excessive transient voltages can disrupt the proper operation of the converter. Because of this possible disruption, the traces in this loop must be wide and short while keeping the loop area as small as possible to reduce the parasitic inductance.

  • Place the input capacitor or capacitors as close as possible to the input pin pairs: VIN1 to PGND1 and VIN2 to PGND2. Place the small capacitors closest. Each pair of pins are adjacent, simplifying the input capacitor placement. With this package, there are two VIN/PGND pairs on either side of the package. This provides a symmetrical layout and helps minimize switching noise and EMI generation. Use a wide VIN plane on a mid-layer to connect both of the VIN pairs together to the input supply. Route symmetrically from the supply to each VIN pin to best use the benefits of the symmetric layout. The 100nF high frequency input capacitors must be placed with 1mm of the VIN and PGND pins of the regulator. (1)
  • Place the bypass capacitor for VCC close to the VCC pin and PGND pin: This capacitor must be routed with short, wide traces to the VCC and PGND pins.
  • Place the BST capacitor as close as possible to the device with short, wide traces to the BST and SW pins:
  • Place the feedback divider as close as possible to the FB pin of the device: Place RFBB, RFBT, CFF if used, physically close to the device. The connections to FB and PGND through RFBB must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator.
  • Place the compensation components as close as possible to the COMP pin: If external compensation components are used, the components must be placed as close to the COMP pin as possible. This action reduces the parasitic capacitance on the COMP pin and help prevent noise pick-up.
  • Layer 2 of the PCB must be a ground plane: This plane acts as a noise shield and as a heat dissipation path. Using layer 2 reduces the inclosed area in the input circulating current in the input loop, reducing inductance.
  • Provide wide paths for VIN, VOUT, and PGND: These paths must be as wide and direct as possible to reduce any voltage drops on the input or output paths of the converter to maximize efficiency.
  • Provide enough PCB area for proper heat sinking or use an external heat sink: Enough copper area must be used to make sure of a low RθJA, considering maximum load current and ambient temperature. Make the top and bottom PCB layers with two-ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note that the package of this device dissipates heat through all pins. Wide traces can be used for all pins except where noise considerations dictate minimization of area. Consider the use of an external heat sink and the mounting requirements.
  • Use generous ground vias: Multiple ground vias must be used (stitching). This action provides both a low impedance ground connection and low impedance heat path for the regulator. This is especially important around the input capacitor grounds. Thermal ground vias are also required under the DAP of the regulator, extending to both side of the PCB. Use the LM654B0EVM as an example. (Figure 8-95 is for illustrative purposes as regards the number and placement of ground vias)
  • Keep switch area small: Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
LM654A5-Q1 LM654B0-Q1 Input Current Loop Figure 8-94 Input Current Loop
1. Input capacitor placement outside of the recommended range can result in device performance degradation including, but not limited to, increased input voltage and switch-node ringing outside of the absolute maximum rating, and system instability.