SNVSCT4B April   2025  – October 2026 LM72880-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for the Serial Control Bus
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulators (VCC, VDDA)
      3. 7.3.3  Enable (EN/UVLO)
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Soft Start
      7. 7.3.7  Output Voltage and Output Voltage Slew Rate
      8. 7.3.8  Minimum Controllable On-Time
      9. 7.3.9  Dual Loop Architecture
        1. 7.3.9.1 Voltage Loop Error Amplifier
        2. 7.3.9.2 Current Loop Error Amplifier
      10. 7.3.10 Programmable OVP
      11. 7.3.11 Programmable ILIM
      12. 7.3.12 IOUT Monitor
      13. 7.3.13 Cable Drop Compensation
      14. 7.3.14 Slope Compensation
      15. 7.3.15 Shunt Current Sensing
      16. 7.3.16 Hiccup Mode Current Limiting
      17. 7.3.17 Device Configuration (CNFG)
      18. 7.3.18 Pulse Frequency Modulation (PFM) / Synchronization
      19. 7.3.19 Out-of-Audio Operation
      20. 7.3.20 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Ready Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Clock Stretching
      3. 7.5.3 Data Transfer Formats
      4. 7.5.4 Single READ from a Defined Register Address
      5. 7.5.5 Sequential READ Starting from a Defined Register Address
      6. 7.5.6 Single WRITE to a Defined Register Address
      7. 7.5.7 Sequential WRITE Starting at a Defined Register Address
  9. 8 LM72880-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
      3. 9.1.3 Maximum Ambient Temperature
        1. 9.1.3.1 Derating Curves
    2. 9.2 Typical Application
      1. 9.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Buck Inductor
          3. 9.2.1.2.3 Current-Sense Resistance
          4. 9.2.1.2.4 Output Capacitors
          5. 9.2.1.2.5 Input Capacitors
          6. 9.2.1.2.6 Compensation Components
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

LM72880-Q1 RRX 29-Pin VQFN (Top View) Figure 5-1 RRX 29-Pin VQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 VIN4 P Converter input pins to the drain of the high-side power MOSFET and the VCC regulator (VIN6). Connect to the input supply and the input filter capacitors. The path from the VIN pin to the input capacitors must be as short as possible.
2 VIN5 P
3 VIN6 P
4 CBOOT P High-side driver supply for the bootstrap gate drive. Connect a 47nF bootstrap capacitor between the CBOOT and SW4 pins.
5 SW4 P Switch pin. Connect a 47nF bootstrap capacitor between the CBOOT and SW4 pins. This pin is internally connected to the switch pins SW1, SW2, and SW3. There is no need to route this pin to the other switch pins on a PCB.
6 SCL I I2C clock pin.
7 SDA I/O I2C data pin.
8 PFM / SYNCIN I PFM / FPWM mode selection and synchronization input pin. Connect the PFM / SYNCIN pin to VDDA to enable diode emulation mode. Connect the PFM / SYNCIN pin to AGND to operate in forced PWM (FPWM) mode with continuous conduction at light loads. The PFM / SYNCIN pin can also be used as a synchronization input to synchronize the internal oscillator to an external clock.
9 EN / UVLO I Enable / undervoltage lockout pin. Drive this pin high / low to enable / disable the device. If the enable function is not needed, tie this pin to VIN. Connect an external resistor divider network to set UVLO threshold.
10 NC N/A No connect pin. Leave floating or tie to GND.
11 ISNS+ A Current sense amplifier input. Connect the ISNS+ pin to the inductor side of the external current sense resistor using a low-current Kelvin connection.
12 VOUTS A Output voltage sense and the current sense amplifier input. Connect the VOUTS pin to the output side of the respective current sense resistor using a low-current Kelvin connection.
13 VOUTF P Output voltage discharge pin and the VCC bias regulator input. Connect the VOUTF pin to the output side of the respective output capacitor.
14 CNFG/ IMON A Configuration and output current monitoring pin. Connect a resistor to ground to set the I2C address and enable or disable the IMON feature. Limit total capacitance on the pin to <200pF.
15 EXTCOMP A External compensation pin. This pin is the output of the transconductance amplifier. Connect a compensation network from the EXTCOMP pin to AGND.
16 nINT O Interrupt pin. This pin is an open-drain output that toggles low in case of a status register change.
17 AGND G Analog ground pin. Ground return for the internal voltage reference and analog circuits.
18 VDDA P Internal analog bias regulator output pin. Connect a 22μF ceramic decoupling capacitor from VDDA to AGND as close as possible to the pins.
19 VCC P VCC bias supply pin. Connect a 4.7μF ceramic capacitor between VCC and PGND as close as possible to the pins.
20 SW1 P Switch pins. These pins form a switching node that is internally connected to the source terminal of the buck switch (high-side MOSFET) and the drain terminal of the synchronous rectifier (low-side MOSFET). Connect to the buck inductor.
21 SW2 P
22 SW3 P
23 PGND1 G Power ground pins. These pins form a power ground node for the low-side MOSFET. Connect to the system ground on a PCB. Path to CIN must be as short as possible.
24 PGND2 G
25 PGND3 G
26 PGND4 G
27 VIN1 P Converter input pins to the drain of the high-side power MOSFET. Connect to the input supply and the input filter capacitors. The path from the VIN pin to the input capacitors must be as short as possible.
28 VIN2 P
29 VIN3 P
30 PGND G Controller power ground pin. Connect to the system ground using multiple vias.
(1) P = Power, G = Ground, I = Input, O = Output, A = Analog.