SNVSCT4B April   2025  – October 2026 LM72880-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for the Serial Control Bus
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulators (VCC, VDDA)
      3. 7.3.3  Enable (EN/UVLO)
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Soft Start
      7. 7.3.7  Output Voltage and Output Voltage Slew Rate
      8. 7.3.8  Minimum Controllable On-Time
      9. 7.3.9  Dual Loop Architecture
        1. 7.3.9.1 Voltage Loop Error Amplifier
        2. 7.3.9.2 Current Loop Error Amplifier
      10. 7.3.10 Programmable OVP
      11. 7.3.11 Programmable ILIM
      12. 7.3.12 IOUT Monitor
      13. 7.3.13 Cable Drop Compensation
      14. 7.3.14 Slope Compensation
      15. 7.3.15 Shunt Current Sensing
      16. 7.3.16 Hiccup Mode Current Limiting
      17. 7.3.17 Device Configuration (CNFG)
      18. 7.3.18 Pulse Frequency Modulation (PFM) / Synchronization
      19. 7.3.19 Out-of-Audio Operation
      20. 7.3.20 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Ready Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Clock Stretching
      3. 7.5.3 Data Transfer Formats
      4. 7.5.4 Single READ from a Defined Register Address
      5. 7.5.5 Sequential READ Starting from a Defined Register Address
      6. 7.5.6 Single WRITE to a Defined Register Address
      7. 7.5.7 Sequential WRITE Starting at a Defined Register Address
  9. 8 LM72880-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
      3. 9.1.3 Maximum Ambient Temperature
        1. 9.1.3.1 Derating Curves
    2. 9.2 Typical Application
      1. 9.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Buck Inductor
          3. 9.2.1.2.3 Current-Sense Resistance
          4. 9.2.1.2.4 Output Capacitors
          5. 9.2.1.2.5 Input Capacitors
          6. 9.2.1.2.6 Compensation Components
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

11 Revision History

Changes from Revision A (December 2025) to Revision B (October 2026)

  • First public release of the full datasheet RTMGo
  • Updated typos and streamlined Features and Description sectionsGo
  • Updated Related Products so that the list includes only Q-grade device optionsGo
  • Changed CONFIG/IMON pin to CNFG/IMON pin in the Pin Configuration and Functions sectionGo
  • Deleted a requirement for a 2MΩ discharge resistor on the EXTCOMP pin in the Pin Configuration and Functions sectionGo
  • Updated pin types for several pins in the Pin Configuration and Functions sectionGo
  • Added separate VOUT ranges for PFM and FPWM modes in Recommended Operating Conditions.Go
  • Added VIN condition to the shutdown current specification; updated typical and maximum specifications.Go
  • Added a maximum limit to the sleep current specification.Go
  • Updated enable voltage rising threshold limits.Go
  • Added TJ = –40°C to +85°C to the test conditions for all VOUT specifications.Go
  • Updated switching frequency limits.Go
  • Updated PG UV/OV limits; added TJ = –40°C to +85°C to the test conditions.Go
  • Updated average current limit setpoint limits; added the TJ = –40°C to +85°C to the test conditions.Go
  • Added TJ = –40°C to +85°C to the test conditions for the output current monitor specifications.Go
  • Added the Typical Characteristics sectionGo
  • Changed VCC regulator output voltage value from 5V to 8V when the output voltage is < 5V in the High-Voltage Bias Supply Regulators sectionGo
  • Updated EN/UVLO threshold values in the Enable (EN/UVLO) sectionGo
  • Added a note about limiting 2.2MHz operation to VIN ≤ 36V in the Switching Frequency sectionGo
  • Added a comment about external synchronization not being possible when DRSS is enabled in the Dual Random Spread Spectrum (DRSS) sectionGo
  • Added SOFT-START SLEW RATE (10mV step size) column to Table 7-3Go
  • Added separate output voltage ranges for PFM and FWPM modes of operation in the Output Voltage Range tableGo
  • Added a comment about selecting CC loop compensation in the Current Loop Error Amplifier sectionGo
  • Added Programmable OVP sectionGo
  • Changed the slope compensation factor from 24 to 40 in the buck inductor equation in the Slope Compensation sectionGo
  • Updated Table 7-6 (CNFG pin does not affect CC regulation any longer)Go
  • Added a comment about limiting mode change rate to < 10Hz in the Pulse Frequency Modulation (PFM) / Synchronization sectionGo
  • Added the Out-of-Audio™ Operation sectionGo
  • Added Programming section and sub-sectionsGo
  • Updated typos and register access types and updated register descriptions in the LM72880-Q1 RegistersGo
  • Added Error Amplifier and Compensation sectionGo
  • Added Maximum Ambient Temperature sectionGo
  • Added the Derating Curves sectionGo
  • Added the Custom Design With WEBENCH® Tools sectionGo
  • Updated typos in the Layout Guidelines sectionGo
  • Added the Custom Design With WEBENCH® Tools sectionGo

Changes from Revision * (April 2025) to Revision A (December 2025)

  • Updated document status from Advance Information to Production DataGo