SPRACH9G November   2021  – December 2024 AWR1443 , AWR1642 , AWR1843 , AWR2544 , AWR2944 , AWR2944P , AWR6843 , AWR6843AOP , AWRL1432 , AWRL6432 , IWR1443 , IWR1642 , IWR1843 , IWR2944 , IWR6443 , IWR6843 , IWR6843AOP , IWRL1432 , IWRL6432

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Definitions, Abbreviations, Acronyms
  5. 2Introduction
  6. 3Serial Data FLASH Supported
    1. 3.1 AWR1243, xWR1443 ES1.0, and ES2.0 Devices
    2. 3.2 AWR294x, AWR2x44P, AWR2544, xWR1642, xWR1843, xWR6843 Devices and AWR1243, xWR1443 ES3.0 Devices
      1. 3.2.1 Prerequisite
      2. 3.2.2 ROM-Assisted Download to the FLASH (Device Management Mode - SOP5)
      3. 3.2.3 ROM-Based Load From FLASH (Functional Mode – SOP4)
      4. 3.2.4 Recommendation
    3. 3.3 Known Issues (xWR1642 ES1.0 and xWR6843 ES1.0 Devices)
    4. 3.4 Flash Variants
      1. 3.4.1 Flash Variants
  7. 4Summary
  8. 5Revision History

3.2.1 Prerequisite

Refer to the device data sheet for details on the timing and interfacing requirements with the SFLASH over the QSPI.

SFLASH device variants must support 40MHz operation for all commands (including normal read command). For the xWR6843 device, the SFLASH device variants need to support 80MHz operation for all commands.

SFLASH supports the SFDP command and responds with JEDEC-compliant information regarding the capabilities and command set of the flash. The key fields interpreted are listed in Table 3-1.

Table 3-1 Key Fields
FieldByte Offset
SFDP signature[3-0]
JEDEC flash parameter offset in bytes[0xE-0xC]
(1-1-4) Read support[JEDEC flash parameter offset in bytes + 0x2] – bit6
(1-1-2) Read support[JEDEC flash parameter offset in bytes + 0x2] – bit0
(1-1-4) Read command code[JEDEC flash parameter offset in bytes + 0xB]
(1-1-4) Read dummy cycles[JEDEC flash parameter offset in bytes + 0xA] – bit[4:0]
(1-1-2) Read command code[JEDEC flash parameter offset in bytes + 0xD]
(1-1-2) Read dummy cycles[JEDEC flash parameter offset in bytes + 0xC] – bit[4:0]
  • The number of address bytes = 3 (always).
  • For single data line SPI read – Read Command Code (0xB), Read Dummy cycles (8bit).