SPRACU1A October   2020  – June 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  3. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  VPP
    8. 2.8  Net Classes
    9. 2.9  DDR4 Signal Termination
    10. 2.10 VREF Routing
    11. 2.11 VTT
    12. 2.12 POD Interconnect
    13. 2.13 CK and ADDR_CTRL Topologies and Routing Guidance
    14. 2.14 Data Group Topologies and Routing Guidance
    15. 2.15 CK and ADDR_CTRL Routing Specification
      1. 2.15.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.15.2 CK and ADDR_CTRL Routing Limits
    16. 2.16 Data Group Routing Specification
      1. 2.16.1 DQLM - DQ Longest Manhattan Distance
      2. 2.16.2 Data Group Routing Limits
    17. 2.17 Bit Swapping
      1. 2.17.1 Data Bit Swapping
      2. 2.17.2 Address and Control Bit Swapping
  4. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  Net Classes
    8. 3.8  LPDDR4 Signal Termination
    9. 3.9  LPDDR4 VREF Routing
    10. 3.10 LPDDR4 VTT
    11. 3.11 CK and ADDR_CTRL Topologies
    12. 3.12 Data Group Topologies
    13. 3.13 CK and ADDR_CTRL Routing Specification
    14. 3.14 Data Group Routing Specification
    15. 3.15 Channel, Byte, and Bit Swapping
  5. 4Revision History

2.8 Net Classes

Routing rules are applied to signals in groups called net classes. Each net class contains signals with the same routing requirements. This simplifies the implementation and compliance of these routes. Table 2-4 lists the clock net classes for the DDR4 interface. Table 2-5 lists the signal net classes, and associated clock net classes, for signals in the DDR4 interface. These net classes are then linked to the termination and routing rules that follow.

Table 2-4 Clock Net Class Definitions
Clock Net Class Processor Pin Names
CK DDR0_CK0 / DDR0_CK0_n
DQS0 DDR0_DQS0 / DDR0_DQS0_n
DQS1 DDR0_DQS1 / DDR0_DQS1_n
Table 2-5 Signal Net Class Definitions
Signal Net Class Associated Clock Net Class Processor Pin Names
ADDR_CTRL CK DDR0_A[13:0], DDR0_WE_n, DDR0_CAS_n, DDR0_RAS_n, DDR0_ACT_n, DDR0_BA0, DDR0_BA1, DDR0_BG0, DDR0_BG1, DDR0_PAR, DDR0_CS0_n, DDR0_CS1_n, DDR0_ODT0, DDR0_ODT1, DDR0_CKE0, DDR0_CKE1
BYTE0 DQS0 DDR0_DQ[7:0], DDR0_DM0
BYTE1 DQS1 DDR0_DQ[15:8], DDR0_DM1