SPRACU1A October   2020  – June 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  3. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  VPP
    8. 2.8  Net Classes
    9. 2.9  DDR4 Signal Termination
    10. 2.10 VREF Routing
    11. 2.11 VTT
    12. 2.12 POD Interconnect
    13. 2.13 CK and ADDR_CTRL Topologies and Routing Guidance
    14. 2.14 Data Group Topologies and Routing Guidance
    15. 2.15 CK and ADDR_CTRL Routing Specification
      1. 2.15.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.15.2 CK and ADDR_CTRL Routing Limits
    16. 2.16 Data Group Routing Specification
      1. 2.16.1 DQLM - DQ Longest Manhattan Distance
      2. 2.16.2 Data Group Routing Limits
    17. 2.17 Bit Swapping
      1. 2.17.1 Data Bit Swapping
      2. 2.17.2 Address and Control Bit Swapping
  4. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  Net Classes
    8. 3.8  LPDDR4 Signal Termination
    9. 3.9  LPDDR4 VREF Routing
    10. 3.10 LPDDR4 VTT
    11. 3.11 CK and ADDR_CTRL Topologies
    12. 3.12 Data Group Topologies
    13. 3.13 CK and ADDR_CTRL Routing Specification
    14. 3.14 Data Group Routing Specification
    15. 3.15 Channel, Byte, and Bit Swapping
  5. 4Revision History

3.14 Data Group Routing Specification

Skew within the Byte signal net class directly reduces the setup and hold margin for the DQ and DM nets. Thus as with the ADDR_CTRL signal net class and associated CK clock net class, this skew must be controlled. The routed PCB track has a delay proportional to its length. Thus, the length skew must be managed through matching the lengths of the routed tracks within a defined group of signals. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock.

Note:

It is not required nor recommended to match the lengths across all byte lanes. Length matching is only required within each byte.

Table 3-7 contains the routing specifications for the Byte0 and Byte1 routing groups. Each signal net class and its associated clock net class is routed and matched independently.

Table 3-7 Data Group Routing Specifications
Number Parameter MIN MAX UNIT
LP4_DRS1 Propagation delay of net class DQSx (RSD1) 500 ps
LP4_DRS2 Propagation delay of net class BYTEx (RSD2) 500 ps
LP4_DRS3 Skew within net class DQSx (DDR0_DQSx to DDR0_DQSx_n skew) 0.4 ps
LP4_DRS4 Skew across net class DQSx and BYTEx (RSD1 to RSD2 skew)(1)(2) 2 ps
LP4_DRS5 Skew within net class BYTEx (DQ/DM to DQ/DM skew)(1) 2 ps
LP4_DRS6 Vias Per Trace 2(4) vias
LP4_DRS7 Via Count Difference 0(3) vias
LP4_DRS8 RSD1 center-to-center spacing (between clock net class)(5) 4w
LP4_DRS9 RSD1 center-to-center spacing (within clock net class)(6)(7) See notes below
LP4_DRS10 RSD2 center-to-center spacing (between signal net class)(5) 4w
LP4_DRS11 RSD2 center-to-center spacing (within signal net class)(5) 3w
(1) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(2) Each DQS pair is length matched to its associated byte.
(3) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure DQn skew and DQSn to DQn skew maximums are not exceeded.
(4) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints).
(6) DQS pair spacing is set to ensure proper differential impedance.
(7) The user must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer.