SPRAD67D September   2024  – October 2025 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
    2. 1.2 Processor-Specific SDK
    3. 1.3 Peripheral Circuit Implementation - Compatibility Between Processor Families
    4. 1.4 Selection of Required Processor OPN (Orderable Part Number)
      1. 1.4.1 Availability of Tightly Coupled Memory (TCM)
      2. 1.4.2 Processor Support for Secure Boot and Functional Safety
    5. 1.5 Technical Documentation
      1. 1.5.1 Updated EVM or SK Schematic With Design, Review and Cad Notes Added
      2. 1.5.2 Collaterals on TI.com, Processor Product Page
      3. 1.5.3 Schematic Design Guidelines and Schematic Review Checklist - Processor Family Specific User's Guide
      4. 1.5.4 Updates to Hardware Design Considerations User's Guide
      5. 1.5.5 Processor and Peripherals Related FAQs to Support Custom Board Designs
    6. 1.6 Custom Board Design Documentation
    7. 1.7 Processor and Processor Peripherals Design Related Queries During Custom Board Design
  5. 2 Custom Board Design Block Diagram
    1. 2.1 Developing the Custom Board Design Block Diagram
    2. 2.2 Configuring the Boot Mode
    3. 2.3 Configuring the Processor Pins Functionality (PinMux Configuration)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power Architecture
      2. 3.1.2 Discrete Power Architecture
    2. 3.2 Processor Supply (Power) Rails (Operating Voltage)
      1. 3.2.1 Core Power Supply
      2. 3.2.2 Peripherals Power Supply
      3. 3.2.3 Dual-Voltage IO Supply for IO Group (Processor) Power Supply
      4. 3.2.4 Integrated LDO for SD Card Interface (Dynamic Voltage Switching Dual-Voltage Power Supply)
      5. 3.2.5 VPP (eFuse ROM Programming) Power Supply
      6. 3.2.6 Internal LDOs for IO Supply for IO Groups (Processor)
    3. 3.3 Power Supply Filtering
    4. 3.4 Power Supply Decoupling and Bulk Capacitors
      1. 3.4.1 Note on PDN Target Impedance
    5. 3.5 Power Supply Sequencing
    6. 3.6 Power Supply Diagnostics (Using Processor Supported External Input Voltage Monitors)
    7. 3.7 Power Supply Diagnostics (Monitoring Using External Monitoring Circuit (Devices))
    8. 3.8 Custom Board Current Requirements Estimation and Supply Sizing
  7. 4 Processor Clock (Input and Output)
    1. 4.1 Processor Clocking (External Crystal or External Oscillator)
      1. 4.1.1 Unused Clock Input
      2. 4.1.2 MCU_OSC0 Crystal Selection
      3. 4.1.3 LVCMOS Compatible Digital Clock Input Source
    2. 4.2 Processor Clock Output
      1. 4.2.1 Observation Clock Outputs
    3. 4.3 Clock Tree Tool
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 BSDL File
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection Recommendations for JTAG Interface Signals
      4. 5.1.4 Debug Boot Modes and Boundary Scan Compliance
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of Processor Boot Mode Configuration Inputs
    3. 6.3 Resetting of the Attached Devices
    4. 6.4 Watchdog Timer
  10. 7 Processor - Peripherals Connection
    1. 7.1  Supported Processor Cores and MCU Cores
    2. 7.2  Selecting Peripherals Across Domains
    3. 7.3  Memory Controller (DDRSS)
      1. 7.3.1 Processor DDR Subsystem and Device Register Configuration
      2. 7.3.2 Calibration Resistor Connection for DDRSS
      3. 7.3.3 Attached Memory Device ZQ and Reset_N (Memory Device Reset) Connection
    4. 7.4  Media and Data Storage Interfaces (MMC0, MMC1, OSPI0/QSPI0 and GPMC0)
    5. 7.5  Ethernet Interface
      1. 7.5.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
      2. 7.5.2 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
    6. 7.6  Universal Serial Bus (USB) Subsystem
    7. 7.7  Peripheral Component Interconnect Express (PCIe) Subsystem
    8. 7.8  General Connectivity Peripherals
      1. 7.8.1 Inter-Integrated Circuit (I2C) Interface
    9. 7.9  Analog-to-Digital Converter (ADC0)
      1. 7.9.1 Change Summary of AM64x, AM243x SR2.0 ADC Errata (FYI only)
    10. 7.10 Connection of Processor Power Supply Pins, IOs and Peripherals When not Used
      1. 7.10.1 External Interrupt (EXTINTn)
      2. 7.10.2 RSVD Reserved Pins (Signals)
    11. 7.11 EVM or SK Specific Circuit Implementation (Reuse)
  11. 8 Interfacing of Processor IOs (LVCMOS or SDIO or Open-Drain, Fail-Safe Type IO Buffers) and Performing Simulations
    1. 8.1 IBIS Model
    2. 8.2 IBIS-AMI Model
  12. 9 Processor Current Draw and Thermal Analysis
    1. 9.1 Power Estimation
      1. 9.1.1 AM64x
      2. 9.1.2 AM243x
    2. 9.2 Maximum Current Rating for Different Supply Rails
      1. 9.2.1 AM64x
      2. 9.2.2 AM243x
    3. 9.3 Supported Device Power States
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 Thermal Model
      2. 9.4.2 Voltage Thermal Management Module (VTM)
  13. 10Schematic:- Capture, Entry and Review
    1. 10.1 Custom Board Design Passive Components and Values Selection
    2. 10.2 Custom Board Design Electronic Computer Aided Design (ECAD) Tools Considerations
    3. 10.3 Custom Board Design Schematic Capture
    4. 10.4 Custom Board Design Schematic Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers, and Simulation
    1. 11.1 Escape Routing for PCB Design
      1. 11.1.1 AM64x
      2. 11.1.2 AM243x
    2. 11.2 DDR Design and Layout Guidelines
    3. 11.3 High-Speed Differential Signal Routing Guidelines
    4. 11.4 Processor-Specific EVM or SK Board Layout
    5. 11.5 Custom Board Layer Count and Layer Stack-up
      1. 11.5.1 Simulation Recommendations
    6. 11.6 DDR-MARGIN-FW
    7. 11.7 Reference for Steps to be Followed for Running Board Simulation
    8. 11.8 Software Development Training (Academy) for Processors
  15. 12Custom Board Assembly and Testing
    1. 12.1 Custom Board Bring-up Tips and Debug Guidelines
  16. 13Processor (Device) Handling and Assembly
    1. 13.1 Processor (Device) Soldering Recommendations
      1. 13.1.1 Additional References
  17. 14References
    1. 14.1 AM64x
    2. 14.2 AM243x
    3. 14.3 Common
  18. 15Terminology
  19. 16Revision History

7.8 General Connectivity Peripherals

The processor families support multiple, general connectivity peripherals and instances. The processor families support the following peripherals:

The following peripherals (universal asynchronous receiver/transmitter (UART), MCAN, multichannel serial port interface (MCSPI), inter-integrated circuit (I2C)) implements IOSET. Make sure the usage of the correct IOSET in the custom board design. Timing closure is based on the IOSETs.

Multichannel Serial Peripheral Interface (MCSPI):

The processor families support x7 (seven) (x5 MAIN domain, x2 MCU domain) instances of MCSPI. The MCSPI module is a multichannel transmit/receive, synchronous serial bus and can operate in controller mode or peripheral mode. In controller mode, the processor SPI sources the clock to the attached device. In peripheral mode, the attached device is required to source the SPI clock to processor.

A series resistor (22Ω) is recommended (as a starting point) for the MCSPI clock output signals. The resistor is recommended to be placed near to the processor clock output pin (used for retiming). A pulldown (10kΩ) is recommended close to the attached device clock input pin.

A pullup (10kΩ) is recommended for the chip select (CS) pin close to the attached device.

The MCSPI peripherals do not support boot. The OSPI0 interface supports SPI boot.

For the MCSPI interface SPIx_D0 and SPIx_D1 are the data lines. The data lines support programming the signals either to transmit data (transmission, output) or receive data (reception, input).

Processor IO buffers are off during reset and after reset. Parallel pulls are recommended for any of the processor IOs (MCSPI interface signals) that can float (to prevent the attached device inputs from floating until driven by the host).

The recommendation is to connect the SPI to x1 (single) memory device. When connecting to multiple memory devices, the recommendation is to follow high-speed design practices and perform simulations to make sure the layout is not going to generate non-monotonic clock transitions when the single clock source is connected to multiple SPI attached devices.

See the following FAQs:

[FAQ] SK-AM64B: MCSPI Integration Guide

[FAQ] AM6412: AM64x SPI D0 and D1 - MISO/MOSI

The FAQ is generic and can also be used for AM243x processor family.

Inter-Integrated Circuit (I2C):

Refer below Section 7.8.1.

Universal Asynchronous Receiver/Transmitter (UART):

The processor families support x9 (nine) (x7 MAIN domain, x2 MCU domain) instances of UART interface. Supported UART functions include data transfer (TXD, RXD), Modem control functions (CTS, RTS) and extended modem control signals (DCD, RI, DTR, DSR - supported by MAIN domain UART0).

Refer to the Signal Descriptions section of the device-specific data sheet for the supported functionalities for each of the UART instances.

Refer to the Timing and Switching Characteristics section of the device-specific data sheet for supported data rate (programmable baud rate).

When external UART interface signals are directly connected to the processor UART interface signals, verify IO level compatibility and fail-safe operation. The recommendation is to provide provision for external ESD protection.

The recommendation is to provision for UART boot (UART0) for early board builds for board bring-up and debug.

Processor IO buffers are off during reset and after reset. Parallel pulls are recommended for any of the processor IOs (UART interface signals) that can float (to prevent the attached device inputs from floating until driven by the host).

General Purpose Input/Output (GPIO):

The processor families support GPIO0, GPIO1 and MCU_GPIO1 instances of GPIO modules. Processor GPIOs include LVCMOS and SDIO buffer types and are push-pull type outputs. Some specific IOs support open-drain output type IO buffer interface. LVCMOS IOs when configured as I (input) have input slew requirements and O (output) has capacitor loading recommendations. The recommendation is to perform simulation with the connected load capacitor to make sure the output is within the ROC as per device-specific data sheet electrical characteristics.

Processor IO buffers are off during reset and after reset. Parallel pulls are recommended for any of the processor IOs that has a trace connected to the processor pads and can float (to prevent the attached device inputs from floating until driven by the host).

For more information, see the following FAQs:

[FAQ] AM625 / AM623 / AM620-Q1 / AM62A / AM62P / AM62D-Q1 / AM62L / AM64x / AM243x Design Recommendations / Custom board hardware design - Queries related to GPIO

[FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM62Ax / AM62D-Q1 / AM62Px / AM64x / AM243x Design Recommendations / Commonly Observed Errors during Custom board hardware design – Queries related to LVCMOS input Hysteresis

[FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM64x/ AM243x (ALV) / AM62Ax / AM62D-Q1 / AM62Px Design Recommendations / Custom board hardware design – Information on PADCONFIG bits and PADCONFIG registers default values summary

Note:

PADCONFIG register bit configuration - ST_EN: The recommendation is to keep the ST_EN bit enabled in case the PADCONFIG register is modified by the software. The minimum Input Slew Rate parameter defined in each Electrical Characteristics table of device-specific data sheet is associated with long-term reliability. The parameters are not a function of the ST_EN bit. The schmitt trigger function implemented in the input buffer only changes the output results of the input buffer, by filtering noise pulses that do not exceed the hysteresis. The schmitt trigger function does not change how the input buffer operates when a system applies a slew rate to its input that is slower than defined in the device-specific data sheet.

Fast Serial Interface (FSI_RX and FSI_TX)

The processor families support x6 (six) (x6 MAIN domain) instances of Fast Serial Interface Receiver (FSI_RX) cores and x2 (two) (x2 MAIN domain) instances of Fast Serial Interface Transmitter (FSI_TX) cores.

For more information, see the following FAQ:

[FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 and AM2434, AM2432, AM2431 (ALV, ALX) Custom board hardware design - FSI Fast Serial Interface

Industrial and Control Interfaces:

The processor families support multiple instances (refer Device Comparison table of the device-specific data sheet) of Industrial and Control Interfaces.

  1. Modular Controller Area Network (MCAN) with Full CAN-FD support
  2. Enhanced Pulse Width Modulator (EPWM)
  3. Enhanced Quadrature Encoder Pulse (EQEP)
  4. Enhanced Capture (ECAP)

Modular Controller Area Network (MCAN) with Full CAN-FD support:

The processor families support x2 (two) (x2 MAIN domain) instances of Modular Controller Area Network (MCAN) with or without Full CAN-FD support.

The MCAN module supports both classic CAN and CAN-FD (CAN with Flexible Data-Rate) specifications. For more information, refer section Device Comparison of device-specific data sheet.

Processor IO buffers are off during reset and after reset. Parallel pulls are recommended for any of the processor IOs (MCAN interface signals) that can float (to prevent the attached device inputs from floating until driven by the host).

Additionally, PRU_ICSSG supports UART0, eCAP0, PWM, IEP0, and IEP1 peripheral modules.

The required interfaces can be configured using the SysConfig-PinMux tool.

For more information on the supported peripherals, see the Peripherals chapter of the device-specific TRM.

Note: AM243x ALX package supports reduced instances of FSI-TX, FSI-RX, UART, MCSPI, I2C and EPWM modules.