SPRADJ1A June   2024  – August 2024 F28377D-SEP , TMS320F280021 , TMS320F280023 , TMS320F280023C , TMS320F280025 , TMS320F280025C , TMS320F280033 , TMS320F280034 , TMS320F280037 , TMS320F280037C , TMS320F280039 , TMS320F280039C , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280049 , TMS320F280049C , TMS320F28075 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2HHC LLC Control Architecture and Logic Diagram
    1. 2.1 CMPSS
    2. 2.2 EPWM
    3. 2.3 Configurable Logic Block (CLB)
  6. 3C2000 Configurations in HHC LLC
    1. 3.1 CMPSS Configurations
    2. 3.2 EPWM Configurations
    3. 3.3 CLB Configurations
  7. 4System Control Method
    1. 4.1 Soft Start
    2. 4.2 Burst Mode Control
    3. 4.3 Minimum and Maximum Frequency Clamping
  8. 5Resonant Capacitor Voltage Sensing Design
  9. 6Summary
  10. 7References
  11. 8Revision History

2.1 CMPSS

CMPSS module receives the control value (Vc) calculated by voltage loop ISR (interrupt service routine), and set to the initial value of the internal ramp generator, which can provide the down-sloped VCR limitation (Vc_ramp) as the DAC value, based on the slope setting. CMPSS module compares the analog signal of VCR, and generates the trigger event (COMPARE_EVT) to trigger the ePWM module through ePWM X-BAR.