SPRSPB5A December   2024  – May 2025 AM62D-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        17
          2.        18
          3.        19
          4.        20
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        23
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  ECAP
        1. 5.3.5.1 MAIN Domain
          1.        32
          2.        33
          3.        34
      7. 5.3.6  Emulation and Debug
        1. 5.3.6.1 MAIN Domain
          1.        37
        2. 5.3.6.2 MCU Domain
          1.        39
      8. 5.3.7  EPWM
        1. 5.3.7.1 MAIN Domain
          1.        42
          2.        43
          3.        44
          4.        45
      9. 5.3.8  EQEP
        1. 5.3.8.1 MAIN Domain
          1.        48
          2.        49
          3.        50
      10. 5.3.9  GPIO
        1. 5.3.9.1 MAIN Domain
          1.        53
          2.        54
        2. 5.3.9.2 MCU Domain
          1.        56
      11. 5.3.10 GPMC
        1. 5.3.10.1 MAIN Domain
          1.        59
      12. 5.3.11 I2C
        1. 5.3.11.1 MAIN Domain
          1.        62
          2.        63
          3.        64
          4.        65
        2. 5.3.11.2 MCU Domain
          1.        67
        3. 5.3.11.3 WKUP Domain
          1.        69
      13. 5.3.12 MCAN
        1. 5.3.12.1 MAIN Domain
          1.        72
        2. 5.3.12.2 MCU Domain
          1.        74
          2.        75
      14. 5.3.13 MCASP
        1. 5.3.13.1 MAIN Domain
          1.        78
          2.        79
          3.        80
      15. 5.3.14 MCSPI
        1. 5.3.14.1 MAIN Domain
          1.        83
          2.        84
          3.        85
        2. 5.3.14.2 MCU Domain
          1.        87
          2.        88
      16. 5.3.15 MDIO
        1. 5.3.15.1 MAIN Domain
          1.        91
      17. 5.3.16 MMC
        1. 5.3.16.1 MAIN Domain
          1.        94
          2.        95
          3.        96
      18. 5.3.17 OSPI
        1. 5.3.17.1 MAIN Domain
          1.        99
      19. 5.3.18 Power Supply
        1.       101
      20. 5.3.19 Reserved
        1.       103
      21. 5.3.20 System and Miscellaneous
        1. 5.3.20.1 Boot Mode Configuration
          1. 5.3.20.1.1 MAIN Domain
            1.         107
        2. 5.3.20.2 Clock
          1. 5.3.20.2.1 MCU Domain
            1.         110
          2. 5.3.20.2.2 WKUP Domain
            1.         112
        3. 5.3.20.3 System
          1. 5.3.20.3.1 MAIN Domain
            1.         115
          2. 5.3.20.3.2 MCU Domain
            1.         117
          3. 5.3.20.3.3 WKUP Domain
            1.         119
        4. 5.3.20.4 VMON
          1.        121
      22. 5.3.21 TIMER
        1. 5.3.21.1 MAIN Domain
          1.        124
        2. 5.3.21.2 MCU Domain
          1.        126
        3. 5.3.21.3 WKUP Domain
          1.        128
      23. 5.3.22 UART
        1. 5.3.22.1 MAIN Domain
          1.        131
          2.        132
          3.        133
          4.        134
          5.        135
          6.        136
          7.        137
        2. 5.3.22.2 MCU Domain
          1.        139
        3. 5.3.22.3 WKUP Domain
          1.        141
      24. 5.3.23 USB
        1. 5.3.23.1 MAIN Domain
          1.        144
          2.        145
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for Devices which are not AEC - Q100 Qualified
    3. 6.3  ESD Ratings for AEC - Q100 Qualified Devices
    4. 6.4  Power-On Hours (POH)
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
    8. 6.8  Electrical Characteristics
      1. 6.8.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.8.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.8.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.8.4 Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.8.5 SDIO Electrical Characteristics
      6. 6.8.6 LVCMOS Electrical Characteristics
      7. 6.8.7 CSI-2 (D-PHY) Electrical Characteristics
      8. 6.8.8 USB2PHY Electrical Characteristics
      9. 6.8.9 DDR Electrical Characteristics
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Thermal Resistance Characteristics for ANF Package
    11. 6.11 Temperature Sensor Characteristics
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Timing Parameters and Information
      2. 6.12.2 Power Supply Requirements
        1. 6.12.2.1 Power Supply Slew Rate Requirement
        2. 6.12.2.2 Power Supply Sequencing
          1. 6.12.2.2.1 Power-Up Sequencing
          2. 6.12.2.2.2 Power-Down Sequencing
          3. 6.12.2.2.3 Partial IO Power Sequencing
      3. 6.12.3 System Timing
        1. 6.12.3.1 Reset Timing
        2. 6.12.3.2 Error Signal Timing
        3. 6.12.3.3 Clock Timing
      4. 6.12.4 Clock Specifications
        1. 6.12.4.1 Input Clocks / Oscillators
          1. 6.12.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
          2. 6.12.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.12.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.12.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.12.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.12.4.2 Output Clocks
        3. 6.12.4.3 PLLs
        4. 6.12.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.12.5 Peripherals
        1. 6.12.5.1  CPSW3G
          1. 6.12.5.1.1 CPSW3G MDIO Timing
          2. 6.12.5.1.2 CPSW3G RMII Timing
          3. 6.12.5.1.3 CPSW3G RGMII Timing
        2. 6.12.5.2  CPTS
        3. 6.12.5.3  CSI-2
        4. 6.12.5.4  DDRSS
        5. 6.12.5.5  ECAP
        6. 6.12.5.6  Emulation and Debug
          1. 6.12.5.6.1 Trace
          2. 6.12.5.6.2 JTAG
        7. 6.12.5.7  EPWM
        8. 6.12.5.8  EQEP
        9. 6.12.5.9  GPIO
        10. 6.12.5.10 GPMC
          1. 6.12.5.10.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.12.5.10.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.12.5.10.3 GPMC and NAND Flash — Asynchronous Mode
        11. 6.12.5.11 I2C
        12. 6.12.5.12 MCAN
        13. 6.12.5.13 MCASP
        14. 6.12.5.14 MCSPI
          1. 6.12.5.14.1 MCSPI — Controller Mode
          2. 6.12.5.14.2 MCSPI — Peripheral Mode
        15. 6.12.5.15 MMCSD
          1. 6.12.5.15.1 MMC0 - eMMC/SD/SDIO Interface
            1. 6.12.5.15.1.1  Legacy SDR Mode
            2. 6.12.5.15.1.2  High Speed SDR Mode
            3. 6.12.5.15.1.3  High Speed DDR Mode
            4. 6.12.5.15.1.4  HS200 Mode
            5. 6.12.5.15.1.5  Default Speed Mode
            6. 6.12.5.15.1.6  High Speed Mode
            7. 6.12.5.15.1.7  UHS–I SDR12 Mode
            8. 6.12.5.15.1.8  UHS–I SDR25 Mode
            9. 6.12.5.15.1.9  UHS–I SDR50 Mode
            10. 6.12.5.15.1.10 UHS–I DDR50 Mode
            11. 6.12.5.15.1.11 UHS–I SDR104 Mode
          2. 6.12.5.15.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.12.5.15.2.1 Default Speed Mode
            2. 6.12.5.15.2.2 High Speed Mode
            3. 6.12.5.15.2.3 UHS–I SDR12 Mode
            4. 6.12.5.15.2.4 UHS–I SDR25 Mode
            5. 6.12.5.15.2.5 UHS–I SDR50 Mode
            6. 6.12.5.15.2.6 UHS–I DDR50 Mode
            7. 6.12.5.15.2.7 UHS–I SDR104 Mode
        16. 6.12.5.16 OSPI
          1. 6.12.5.16.1 OSPI0 PHY Mode
            1. 6.12.5.16.1.1 OSPI0 With PHY Data Training
            2. 6.12.5.16.1.2 OSPI0 Without Data Training
              1. 6.12.5.16.1.2.1 OSPI0 PHY SDR Timing
              2. 6.12.5.16.1.2.2 OSPI0 PHY DDR Timing
          2. 6.12.5.16.2 OSPI0 Tap Mode
            1. 6.12.5.16.2.1 OSPI0 Tap SDR Timing
            2. 6.12.5.16.2.2 OSPI0 Tap DDR Timing
        17. 6.12.5.17 Timers
        18. 6.12.5.18 UART
        19. 6.12.5.19 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem
      2. 7.2.2 Device/Power Manager
      3. 7.2.3 MCU Arm Cortex-R5F Subsystem
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 C7x256V DSP with Matrix Multiplication Accelerator
    4. 7.4 Other Subsystems
      1. 7.4.1 Dual Clock Comparator (DCC)
      2. 7.4.2 Data Movement Subsystem (DMSS)
      3. 7.4.3 Memory Cyclic Redundancy Check (MCRC)
      4. 7.4.4 Peripheral DMA Controller (PDMA)
      5. 7.4.5 Real-Time Clock (RTC)
    5. 7.5 Peripherals
      1. 7.5.1  Gigabit Ethernet Switch (CPSW3G)
      2. 7.5.2  Camera Serial Interface Receiver (CSI_RX_IF)
      3. 7.5.3  Enhanced Capture (ECAP)
      4. 7.5.4  Error Location Module (ELM)
      5. 7.5.5  Enhanced Pulse Width Modulation (EPWM)
      6. 7.5.6  Error Signaling Module (ESM)
      7. 7.5.7  Enhanced Quadrature Encoder Pulse (EQEP)
      8. 7.5.8  General-Purpose Interface (GPIO)
      9. 7.5.9  General-Purpose Memory Controller (GPMC)
      10. 7.5.10 Global Timebase Counter (GTC)
      11. 7.5.11 Inter-Integrated Circuit (I2C)
      12. 7.5.12 Modular Controller Area Network (MCAN)
      13. 7.5.13 Multichannel Audio Serial Port (MCASP)
      14. 7.5.14 Multichannel Serial Peripheral Interface (MCSPI)
      15. 7.5.15 Multi-Media Card Secure Digital (MMCSD)
      16. 7.5.16 Octal Serial Peripheral Interface (OSPI)
      17. 7.5.17 Timers
      18. 7.5.18 Universal Asynchronous Receiver/Transmitter (UART)
      19. 7.5.19 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
Table 5-22 GPIO1 Signal Descriptions
SIGNAL NAME [1]PIN TYPE [2]DESCRIPTION [3]ANF PIN [4]
GPIO1_0IOGeneral Purpose Input/OutputW17
GPIO1_1IOGeneral Purpose Input/OutputW18
GPIO1_2IOGeneral Purpose Input/OutputAA20
GPIO1_3IOGeneral Purpose Input/OutputAA21
GPIO1_4IOGeneral Purpose Input/OutputY20
GPIO1_5IOGeneral Purpose Input/OutputAB21
GPIO1_6IOGeneral Purpose Input/OutputAB20
GPIO1_7IOGeneral Purpose Input/OutputC19
GPIO1_8IOGeneral Purpose Input/OutputB19
GPIO1_9IOGeneral Purpose Input/OutputB18
GPIO1_10IOGeneral Purpose Input/OutputB20
GPIO1_11IOGeneral Purpose Input/OutputA19
GPIO1_12IOGeneral Purpose Input/OutputA20
GPIO1_13IOGeneral Purpose Input/OutputB21
GPIO1_14IOGeneral Purpose Input/OutputA21
GPIO1_15IOGeneral Purpose Input/OutputD16
GPIO1_16 (1)IOGeneral Purpose Input/OutputC16
GPIO1_17IOGeneral Purpose Input/OutputA17
GPIO1_18IOGeneral Purpose Input/OutputB15
GPIO1_19IOGeneral Purpose Input/OutputE15
GPIO1_20IOGeneral Purpose Input/OutputE14
GPIO1_21IOGeneral Purpose Input/OutputD15
GPIO1_22IOGeneral Purpose Input/OutputF14
GPIO1_23IOGeneral Purpose Input/OutputC15
GPIO1_24IOGeneral Purpose Input/OutputB17
GPIO1_25IOGeneral Purpose Input/OutputC18
GPIO1_26IOGeneral Purpose Input/OutputD17
GPIO1_27IOGeneral Purpose Input/OutputE16
GPIO1_28IOGeneral Purpose Input/OutputC17
GPIO1_29IOGeneral Purpose Input/OutputE17
GPIO1_30IOGeneral Purpose Input/OutputB16
GPIO1_31 (1)IOGeneral Purpose Input/OutputF17
GPIO1_32 (1)IOGeneral Purpose Input/OutputAB8
GPIO1_33 (1)IOGeneral Purpose Input/OutputW9
GPIO1_34 (1)IOGeneral Purpose Input/OutputW7
GPIO1_35 (1)IOGeneral Purpose Input/OutputY8
GPIO1_36 (1)IOGeneral Purpose Input/OutputAA7
GPIO1_37 (1)IOGeneral Purpose Input/OutputY7
GPIO1_38 (1)IOGeneral Purpose Input/OutputAB6
GPIO1_39 (1)IOGeneral Purpose Input/OutputAA6
GPIO1_40 (1)IOGeneral Purpose Input/OutputAB7
GPIO1_41 (1)IOGeneral Purpose Input/OutputY6
GPIO1_42 (1)IOGeneral Purpose Input/OutputD22
GPIO1_43 (1)IOGeneral Purpose Input/OutputC22
GPIO1_44 (1)IOGeneral Purpose Input/OutputD21
GPIO1_45 (1)IOGeneral Purpose Input/OutputB22
GPIO1_46 (1)IOGeneral Purpose Input/OutputE22
GPIO1_47 (1)IOGeneral Purpose Input/OutputC21
GPIO1_48 (1)IOGeneral Purpose Input/OutputE18
GPIO1_49 (1)IOGeneral Purpose Input/OutputD18
GPIO1_50IOGeneral Purpose Input/OutputC20
GPIO1_51IOGeneral Purpose Input/OutputD19
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter.