SPRSPC3 February   2026 AM13E23019

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1.      Device Package Options
      2. 5.1.1 AM13E230x Pin Diagrams
    2. 5.2 Pin Attributes
      1. 5.2.1 Pin Attributes Header List
      2.      13
    3. 5.3 Signal Descriptions
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      36.      50
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings – Commercial
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Digital IO
    6. 6.6 Analog Peripherals
      1. 6.6.1 Analog-to-Digital Converter (ADC)
      2. 6.6.2 ADC Characteristics
        1. 6.6.2.1 ADC Operating Conditions
        2. 6.6.2.2 ADC Electrical Data and Timing
        3. 6.6.2.3 External ADC Start-of-Conversion Switching Characteristics
      3. 6.6.3 Comparator Subsystem (CMPSS)
      4. 6.6.4 CMPSS Electrical Data and Timing
        1. 6.6.4.1 CMPSS_LITE Comparator Electrical Characteristics
        2. 6.6.4.2 CMPSS_LITE DAC Static Electrical Characteristics
      5. 6.6.5 Programmable Gain Amplifier (PGA)
      6. 6.6.6 PGA Electrical Data and Timing
        1. 6.6.6.1 PGA Operating Conditions
        2. 6.6.6.2 PGA Characteristics
      7. 6.6.7 Temperature Sensor Characteristics
      8.      Internal Analog Connections
    7. 6.7 Control Peripherals
      1. 6.7.1 Multichannel Pulse Width Modulator (MCPWM)
      2. 6.7.2 Control Peripherals Synchronization
      3. 6.7.3 MCPWM Electrical Data and Timing
        1. 6.7.3.1 MCPWM Timing Requirements
        2. 6.7.3.2 MCPWM Switching Characteristics
      4. 6.7.4 Enhanced Capture eCAP
      5. 6.7.5 eCAP Block Diagram
      6. 6.7.6 eCAP Synchronization
      7. 6.7.7 eCAP Electrical Data and Timing
        1. 6.7.7.1 eCAP Timing Requirements
        2. 6.7.7.2 eCAP Switching Characteristics
      8. 6.7.8 Enhanced Quadrature Encoder Pulse (eQEP)
      9. 6.7.9 eQEP Electrical Data and Timing
        1. 6.7.9.1 eQEP Timing Requirements
        2. 6.7.9.2 eQEP Switching Characteristics
    8. 6.8 Communication Peripherals
      1. 6.8.1 Modular Controller Area Network (MCAN)
  8. 7 Detailed Description
    1. 7.1  Description
      1. 7.1.1 Functional Block Diagram
    2. 7.2  Memory
      1. 7.2.1 Peripheral Registers Memory Map
      2. 7.2.2 Static RAM
      3. 7.2.3 Flash Memory
    3. 7.3  Identification
    4. 7.4  Arm Cortex-M33 CPU
      1. 7.4.1 Trigonometric Math Unit (TMU)
      2. 7.4.2 Debug Subsystem
    5. 7.5  TinyEngineTM Neural-network Processing Unit (NPU)
    6. 7.6  DMA
    7. 7.7  Error Aggregator Module (EAM)
    8. 7.8  Power Management and Clock Unit (PMCU)
      1. 7.8.1 Power Management Unit (PMU)
      2. 7.8.2 Operating Modes
        1. 7.8.2.1 Functionality by Operating Mode
      3. 7.8.3 Clock Module (CKM)
    9. 7.9  UNICOMM (UART/I2C/SPI)
      1. 7.9.1 Universal Asychronous Receiver/Transmitter (UART)
      2. 7.9.2 Inter-Integrated Circuit (I2C)
      3. 7.9.3 Serial Peripheral Interface (SPI)
    10. 7.10 CAN-FD
    11. 7.11 Serial Wire Debug Interface
    12. 7.12 External Peripheral Interface (EPI)
    13. 7.13 Bootstrap Loader (BSL)
    14. 7.14 Security
      1. 7.14.1 Global Security Controller
      2. 7.14.2 AESADV
      3. 7.14.3 Keystore Controller
    15. 7.15 Timers (TIMx)
    16. 7.16 WWDT
  9. 8 Applications, Implementation, and Layout
    1. 8.1 External Oscillator
    2. 8.2 JTAG and TRACE
    3. 8.3 Application and Implementation
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Nomenclature
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.14.2 AESADV

The AESADV accelerator module performs encryption and decryption of 128-bit data blocks with 128-bit or 256-bit keys in hardware according to the Advanced Encryption Standard (AES).