SPRSPC3A
February 2026 – August 2026
AM13E23019
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
3.1
Functional Block Diagram
4
Device Comparison
5
Terminal Configuration and Functions
5.1
Pin Diagram
Device Package Options
5.2
AM13E230x Pin Diagrams
5.3
Pin Attributes
5.3.1
Pin Attributes Header List
13
5.4
Signal Descriptions
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
5.5
Pin Connectivity Requirements
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings – Commercial
6.3
Recommended Operating Conditions
6.4
Supply Current Characteristics
6.4.1
RUN/SLEEP Modes
6.4.2
STOP/STANDBY Modes
6.4.3
SHUTDOWN Mode
6.4.4
Reducing Current Consumption
6.4.4.1
Typical Current Reduction per Disabled Peripheral
6.5
Electrical Characteristics
6.6
Digital IO
6.7
Thermal Information
6.8
System
6.8.1
Power Supply Sequencing
6.8.1.1
Power Supply Ramp
6.8.1.2
POR and BOR
6.8.1.2.1
POR and BOR
6.8.1.3
Timing Characteristics
6.8.1.3.1
Timing Characteristics
6.8.2
Clock Module (CKM)
6.8.2.1
System Oscillator (SYSOSC)
6.8.2.2
High Frequency Crystal/Clock
6.8.2.3
System Phase Lock Loop (SYSPLL)
6.8.2.4
Low Frequency Oscillator (LFOSC)
6.8.3
Flash Memory Characteristics
6.8.3.1
Flash Memory Characteristics
6.8.4
RAM Specifications
6.8.5
ROM Specifications
6.9
Analog Peripherals
6.9.1
Analog-to-Digital Converter (ADC)
6.9.1.1
ADC Electrical Data and Timing
6.9.1.1.1
ADC Operating Conditions
6.9.1.1.2
ADC Characteristics
6.9.1.1.3
ADC Input Model
ADC Input Model
6.9.1.1.4
ADC Timing Requirements
6.9.1.1.5
External ADC Start-of-Conversion Switching Characteristics
6.9.2
Comparator Subsystem (CMPSS)
6.9.2.1
CMPSS Electrical Data and Timing
6.9.2.1.1
CMPSS_LITE Comparator Electrical Characteristics
6.9.2.1.2
CMPSS_LITE DAC Static Electrical Characteristics
6.9.3
Programmable Gain Amplifier (PGA)
6.9.3.1
PGA Electrical Data and Timing
6.9.3.1.1
PGA Operating Conditions
6.9.3.1.2
PGA Characteristics
6.9.4
Temperature Sensor
6.9.4.1
Temperature Sensor Electrical Data and Timing
6.9.4.2
Temperature Sensor Characteristics
6.9.5
Internal Analog Connections
6.10
Control Peripherals
6.10.1
Multichannel Pulse Width Modulator (MCPWM)
6.10.2
Control Peripherals Synchronization
6.10.3
MCPWM Electrical Data and Timing
6.10.3.1
MCPWM Timing Requirements
6.10.3.2
MCPWM Switching Characteristics
6.10.4
Enhanced Capture eCAP
6.10.5
eCAP Block Diagram
6.10.6
eCAP Synchronization
6.10.7
eCAP Electrical Data and Timing
6.10.7.1
eCAP Timing Requirements
6.10.7.2
eCAP Switching Characteristics
6.10.8
Enhanced Quadrature Encoder Pulse (eQEP)
6.10.9
eQEP Electrical Data and Timing
6.10.9.1
eQEP Timing Requirements
6.10.9.2
eQEP Switching Characteristics
6.11
Communication Peripherals
6.11.1
UNICOMM (UART/I2C/SPI)
6.11.1.1
Universal Asychronous Receiver/Transmitter (UART)
6.11.1.1.1
UART Timings and Characteristics
6.11.1.2
Inter-Integrated Circuit (I2C)
6.11.1.2.1
I2C Timings and Characteristics
6.11.1.2.2
I2C Filter Timings
6.11.1.2.3
I2C Timing Diagram
6.11.1.3
Serial Peripheral Interface (SPI)
6.11.1.3.1
SPI Timings and Characteristics
6.11.1.3.2
SPI Timing Diagram
6.11.2
Modular Controller Area Network (MCAN)
6.11.2.1
CAN Timings and Characteristics
6.12
External Peripheral Interface (EPI)
6.12.1
EPI SDRAM Interface Switching Characteristics
6.12.2
EPI SDRAM Timing Diagram
6.12.3
EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics
6.12.4
EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements
6.12.5
EPI Host-Bus 8/16 Mode Timing Diagram
6.12.6
EPI General-Purpose Interface Switching Characteristics
6.12.7
EPI General-Purpose Interface Timing Requirements
6.12.8
EPI General-Purpose Mode Timing Diagram
6.13
Emulation and Debug
6.13.1
SWD Timing
7
Detailed Description
7.1
Overview
7.2
Memory
7.2.1
Memory Map
7.2.2
Peripheral Registers Memory Map
7.2.3
Static RAM
7.2.4
Flash Memory
7.3
Identification
7.4
Arm Cortex-M33 CPU
7.4.1
Trigonometric Math Unit (TMU)
7.4.2
Debug Subsystem
7.5
TinyEngineTM Neural-network Processing Unit (NPU)
7.6
DMA
7.7
Error Aggregator Module (EAM)
7.8
Power Management and Clock Unit (PMCU)
7.8.1
Power Management Unit (PMU)
7.8.2
Operating Modes
7.8.2.1
Functionality by Operating Mode
7.8.3
Clock Module (CKM)
7.9
IOMUX
7.9.1
Input/Output Diagrams
7.10
Serial Wire Debug Interface
7.11
Bootstrap Loader (BSL)
7.12
Security
7.12.1
Global Security Controller (GSC)
7.12.2
AESADV
7.12.3
Keystore Controller
7.12.4
CRC Accelerator
7.13
Timers (TIMx)
7.14
WWDT
8
Applications, Implementation, and Layout
8.1
JTAG and TRACE
8.2
Schematic
8.3
Typical Applications
9
Device and Documentation Support
9.1
Third-Party Products Disclaimer
9.2
Device Nomenclature
9.3
Markings
9.4
Tools and Software
9.5
Documentation Support
9.6
Support Resources
9.7
Trademarks
9.8
Electrostatic Discharge Caution
9.9
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
PACKAGE OPTION ADDENDUM
6.10
Control Peripherals