SPRSPC3A February   2026  – August 2026 AM13E23019

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2.     Device Package Options
    3. 5.2 AM13E230x Pin Diagrams
    4. 5.3 Pin Attributes
      1. 5.3.1 Pin Attributes Header List
      2.      13
    5. 5.4 Signal Descriptions
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    6. 5.5 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Supply Current Characteristics
      1. 6.4.1 RUN/SLEEP Modes
      2. 6.4.2 STOP/STANDBY Modes
      3. 6.4.3 SHUTDOWN Mode
      4. 6.4.4 Reducing Current Consumption
        1. 6.4.4.1 Typical Current Reduction per Disabled Peripheral
    5. 6.5  Electrical Characteristics
    6. 6.6  Digital IO
    7. 6.7  Thermal Information
    8. 6.8  System
      1. 6.8.1 Power Supply Sequencing
        1. 6.8.1.1 Power Supply Ramp
        2. 6.8.1.2 POR and BOR
          1. 6.8.1.2.1 POR and BOR
        3. 6.8.1.3 Timing Characteristics
          1. 6.8.1.3.1 Timing Characteristics
      2. 6.8.2 Clock Module (CKM)
        1. 6.8.2.1 System Oscillator (SYSOSC)
        2. 6.8.2.2 High Frequency Crystal/Clock
        3. 6.8.2.3 System Phase Lock Loop (SYSPLL)
        4. 6.8.2.4 Low Frequency Oscillator (LFOSC)
      3. 6.8.3 Flash Memory Characteristics
        1. 6.8.3.1 Flash Memory Characteristics
      4. 6.8.4 RAM Specifications
      5. 6.8.5 ROM Specifications
    9. 6.9  Analog Peripherals
      1. 6.9.1 Analog-to-Digital Converter (ADC)
        1. 6.9.1.1 ADC Electrical Data and Timing
          1. 6.9.1.1.1 ADC Operating Conditions
          2. 6.9.1.1.2 ADC Characteristics
          3. 6.9.1.1.3 ADC Input Model
            1.         ADC Input Model
          4. 6.9.1.1.4 ADC Timing Requirements
          5. 6.9.1.1.5 External ADC Start-of-Conversion Switching Characteristics
      2. 6.9.2 Comparator Subsystem (CMPSS)
        1. 6.9.2.1 CMPSS Electrical Data and Timing
          1. 6.9.2.1.1 CMPSS_LITE Comparator Electrical Characteristics
          2. 6.9.2.1.2 CMPSS_LITE DAC Static Electrical Characteristics
      3. 6.9.3 Programmable Gain Amplifier (PGA)
        1. 6.9.3.1 PGA Electrical Data and Timing
          1. 6.9.3.1.1 PGA Operating Conditions
          2. 6.9.3.1.2 PGA Characteristics
      4. 6.9.4 Temperature Sensor
        1. 6.9.4.1 Temperature Sensor Electrical Data and Timing
        2. 6.9.4.2 Temperature Sensor Characteristics
      5. 6.9.5 Internal Analog Connections
    10. 6.10 Control Peripherals
      1. 6.10.1 Multichannel Pulse Width Modulator (MCPWM)
      2. 6.10.2 Control Peripherals Synchronization
      3. 6.10.3 MCPWM Electrical Data and Timing
        1. 6.10.3.1 MCPWM Timing Requirements
        2. 6.10.3.2 MCPWM Switching Characteristics
      4. 6.10.4 Enhanced Capture eCAP
      5. 6.10.5 eCAP Block Diagram
      6. 6.10.6 eCAP Synchronization
      7. 6.10.7 eCAP Electrical Data and Timing
        1. 6.10.7.1 eCAP Timing Requirements
        2. 6.10.7.2 eCAP Switching Characteristics
      8. 6.10.8 Enhanced Quadrature Encoder Pulse (eQEP)
      9. 6.10.9 eQEP Electrical Data and Timing
        1. 6.10.9.1 eQEP Timing Requirements
        2. 6.10.9.2 eQEP Switching Characteristics
    11. 6.11 Communication Peripherals
      1. 6.11.1 UNICOMM (UART/I2C/SPI)
        1. 6.11.1.1 Universal Asychronous Receiver/Transmitter (UART)
          1. 6.11.1.1.1 UART Timings and Characteristics
        2. 6.11.1.2 Inter-Integrated Circuit (I2C)
          1. 6.11.1.2.1 I2C Timings and Characteristics
          2. 6.11.1.2.2 I2C Filter Timings
          3. 6.11.1.2.3 I2C Timing Diagram
        3. 6.11.1.3 Serial Peripheral Interface (SPI)
          1. 6.11.1.3.1 SPI Timings and Characteristics
          2. 6.11.1.3.2 SPI Timing Diagram
      2. 6.11.2 Modular Controller Area Network (MCAN)
        1. 6.11.2.1 CAN Timings and Characteristics
    12. 6.12 External Peripheral Interface (EPI)
      1. 6.12.1 EPI SDRAM Interface Switching Characteristics
      2. 6.12.2 EPI SDRAM Timing Diagram
      3. 6.12.3 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics
      4. 6.12.4 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements
      5. 6.12.5 EPI Host-Bus 8/16 Mode Timing Diagram
      6. 6.12.6 EPI General-Purpose Interface Switching Characteristics
      7. 6.12.7 EPI General-Purpose Interface Timing Requirements
      8. 6.12.8 EPI General-Purpose Mode Timing Diagram
    13. 6.13 Emulation and Debug
      1. 6.13.1 SWD Timing
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Memory
      1. 7.2.1 Memory Map
      2. 7.2.2 Peripheral Registers Memory Map
      3. 7.2.3 Static RAM
      4. 7.2.4 Flash Memory
    3. 7.3  Identification
    4. 7.4  Arm Cortex-M33 CPU
      1. 7.4.1 Trigonometric Math Unit (TMU)
      2. 7.4.2 Debug Subsystem
    5. 7.5  TinyEngineTM Neural-network Processing Unit (NPU)
    6. 7.6  DMA
    7. 7.7  Error Aggregator Module (EAM)
    8. 7.8  Power Management and Clock Unit (PMCU)
      1. 7.8.1 Power Management Unit (PMU)
      2. 7.8.2 Operating Modes
        1. 7.8.2.1 Functionality by Operating Mode
      3. 7.8.3 Clock Module (CKM)
    9. 7.9  IOMUX
      1. 7.9.1 Input/Output Diagrams
    10. 7.10 Serial Wire Debug Interface
    11. 7.11 Bootstrap Loader (BSL)
    12. 7.12 Security
      1. 7.12.1 Global Security Controller (GSC)
      2. 7.12.2 AESADV
      3. 7.12.3 Keystore Controller
      4. 7.12.4 CRC Accelerator
    13. 7.13 Timers (TIMx)
    14. 7.14 WWDT
  9. 8 Applications, Implementation, and Layout
    1. 8.1 JTAG and TRACE
    2. 8.2 Schematic
    3. 8.3 Typical Applications
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13.   PACKAGE OPTION ADDENDUM

6.10.4 Enhanced Capture eCAP

The features of the eCAP module include:

  • Speed measurements of rotating machinery (for example, toothed sprockets sensed by way of Hall sensors)
  • Elapsed time measurements between position sensor pulses
  • Period and duty cycle measurements of pulse train signals
  • Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors

The eCAP module features described in this section include:

  • 4-event time-stamp registers (each 32 bits)
  • Edge polarity selection for up to four sequenced time-stamp capture events
  • Interrupt on either of the four events
  • Single-shot capture of up to four event time-stamps
  • Continuous mode capture of time stamps in a four-deep circular buffer
  • Absolute time-stamp capture
  • Difference (Delta) mode time-stamp capture
  • When not used in capture mode, the eCAP module can be configured as a single-channel PWM output

The capture functionality of the Type 1 eCAP is enhanced from the Type 0 eCAP with the following added features:

  • Event filter reset bit
    • Writing a 1 to ECCTL2[CTRFILTRESET] clears the event filter, the modulo counter, and any pending interrupts flags. Resetting the bit is useful for initialization and debug.
  • Modulo counter status bits
    • The modulo counter (ECCTL2 [MODCNTRSTS]) indicates which capture register is loaded next. In the Type 0 eCAP, to know the current state of the modulo counter was not possible
  • DMA trigger source
    • eCAPxDMA was added as a DMA trigger. CEVT[1-4] can be configured as the source for eCAPxDMA.
  • Input multiplexer
    • ECCTL0 [INPUTSEL] selects one of 128 input signals, which are detailed in the Configuring Device Pins for the eCAP section of the Enhanced Capture (eCAP) chapter in the TRM.
  • EALLOW protection
    • EALLOW protection was added to critical registers. To maintain software compatibility with Type-0, configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.

The capture functionality of the Type 2 eCAP is enhanced from the Type 1 eCAP with the following added features:

  • Added ECAPxSYNCINSEL register
    • ECAPxSYNCINSEL register is added for each eCAP to select an external SYNCIN. Every eCAP can have a separate SYNCIN signal.