The external peripheral interface (EPI) is a high-speed parallel bus for external peripherals or memory. The module has several modes of operation to interface seamlessly to many types of external devices. The EPI is similar to a standard microprocessor address/data bus, except that it must typically be connected to just one type of external device. Enhanced capabilities include DMA support, clocking control and support for external FIFO buffers.

The EPI has the following features:

• 8/16/32-bit dedicated parallel bus for external peripherals and memory
• Memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from SDRAM, SRAM and Flash memory
• Blocking and non-blocking reads
• Separates processor from timing details through use of an internal write FIFO
• Efficient transfers using Direct Memory Access (DMA) Controller
  • Separate channels for read and write
  • Read channel request asserted by programmable levels on the internal non-blocking read FIFO (NBRFIFO)
  • Write channel request asserted by empty on the internal write FIFO (WFIFO)

The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory (SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same way as a communication mechanism and is speed-controlled using clocking.

• Synchronous Dynamic Random Access Memory (SDRAM)
  • Supports x16 (single data rate) SDRAM at up to 50MHz
  • Supports low-cost SDRAMs up to 64 MB (512 megabits)
  • Includes automatic refresh and access to all banks/rows
  • Includes a Sleep/Standby mode to keep contents active with minimal power draw
  • Multiplexed address/data interface for reduced pin count
• Host-bus
  • Traditional x8 and x16 MCU bus interface capabilities
  • Similar device compatibility options as PIC, ATmega, 8051, and others
  • Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in non-multiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with no byte selects)
  • Support of both muxed and de-muxed address and data
  • Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant, with support for external FIFO (XFIFO) EMPTY and FULL signals
  • Speed controlled, with read and write data wait-state counters
  • Support for read/write burst mode to Host Bus
  • Multiple chip select modes including single, dual, and quad chip selects, with and without ALE
  • External iRDY signal provided for stall capability of reads and writes
  • Manual chip-enable (or use extra address pins)
• General Purpose
  • Wide parallel interfaces for fast communications with CPLDs and FPGAs
  • Data widths up to 32 bits
  • Data rates up to 125 MB/second
  • Optional "address" sizes from 4 bits to 20 bits
  • Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input
• General parallel GPIO
  • 1 to 32 bits, FIFOed with speed control
  • Useful for custom peripherals or for digital data acquisition and actuator controls